From eba05254cb561dc27d5664503f91f7c21954e648 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 31 Mar 2009 14:54:19 -0700 Subject: [PATCH] REMOVE OMAP LEGACY CODE: Reset clocks and PM code to mainline This is to avoid serious merge conflicts when pulling from mainline. With tons of the clock patches now in the mainline, it's a good time to switch over to using the mainline code for clocks and PM. The remaining clock and pm patches will be merged back in from Paul's clock branch, and Kevin's pm branch. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/clock.c | 359 +-- arch/arm/mach-omap1/clock.h | 354 +-- arch/arm/mach-omap1/mailbox.c | 8 +- arch/arm/mach-omap1/mcbsp.c | 52 +- arch/arm/mach-omap2/Makefile | 6 - arch/arm/mach-omap2/board-3430sdp-flash.c | 21 + arch/arm/mach-omap2/board-3430sdp.c | 2 + arch/arm/mach-omap2/board-n800-usb.c | 4 +- arch/arm/mach-omap2/board-n800.c | 1 + arch/arm/mach-omap2/board-omap2evm.c | 6 +- arch/arm/mach-omap2/board-omap3evm-flash.c | 2 + arch/arm/mach-omap2/board-omap3evm.c | 8 + arch/arm/mach-omap2/board-overo.c | 3 + arch/arm/mach-omap2/board-rx51-flash.c | 1 + arch/arm/mach-omap2/board-rx51.c | 1 + arch/arm/mach-omap2/clock.c | 383 ++-- arch/arm/mach-omap2/clock.h | 16 +- arch/arm/mach-omap2/clock24xx.c | 358 ++- arch/arm/mach-omap2/clock24xx.h | 1294 ++++------- arch/arm/mach-omap2/clock34xx.c | 429 +++- arch/arm/mach-omap2/clock34xx.h | 1966 ++++++----------- arch/arm/mach-omap2/clockdomain.c | 22 +- arch/arm/mach-omap2/clockdomains.h | 19 +- arch/arm/mach-omap2/cm-regbits-24xx.h | 1 - arch/arm/mach-omap2/cm.h | 16 +- arch/arm/mach-omap2/devices.c | 6 +- arch/arm/mach-omap2/io.c | 1 + arch/arm/mach-omap2/irq.c | 20 - arch/arm/mach-omap2/mailbox.c | 38 +- arch/arm/mach-omap2/mcbsp.c | 26 - arch/arm/mach-omap2/pm-debug.c | 156 -- arch/arm/mach-omap2/pm.c | 152 +- arch/arm/mach-omap2/pm.h | 34 - arch/arm/mach-omap2/pm24xx.c | 560 ----- arch/arm/mach-omap2/pm34xx.c | 734 ------ arch/arm/mach-omap2/prcm-common.h | 2 - arch/arm/mach-omap2/prcm.c | 14 +- arch/arm/mach-omap2/prm-regbits-34xx.h | 27 +- arch/arm/mach-omap2/prm.h | 142 +- arch/arm/mach-omap2/sdrc.c | 5 +- arch/arm/mach-omap2/sdrc2xxx.c | 11 +- arch/arm/mach-omap2/serial.c | 435 +--- arch/arm/mach-omap2/sleep34xx.S | 544 ----- arch/arm/mach-omap2/smartreflex.c | 762 ------- arch/arm/mach-omap2/smartreflex.h | 259 --- arch/arm/mach-omap2/sram242x.S | 5 - arch/arm/mach-omap2/sram243x.S | 5 - arch/arm/mach-omap2/timer-gp.c | 5 +- arch/arm/plat-omap/Kconfig | 49 +- arch/arm/plat-omap/clock.c | 371 +--- arch/arm/plat-omap/cpu-omap.c | 2 +- arch/arm/plat-omap/devices.c | 5 +- .../plat-omap/include/mach/board-3430sdp.h | 58 - .../plat-omap/include/mach/board-omap2evm.h | 38 - .../include/mach/board-omap3beagle.h | 33 - .../plat-omap/include/mach/board-omap3evm.h | 44 - .../plat-omap/include/mach/board-voiceblue.h | 1 - arch/arm/plat-omap/include/mach/clkdev.h | 13 + arch/arm/plat-omap/include/mach/clock.h | 123 +- arch/arm/plat-omap/include/mach/common.h | 7 +- arch/arm/plat-omap/include/mach/control.h | 32 - arch/arm/plat-omap/include/mach/hardware.h | 42 - arch/arm/plat-omap/include/mach/mcbsp.h | 26 +- arch/arm/plat-omap/include/mach/omap-alsa.h | 36 +- arch/arm/plat-omap/include/mach/omap34xx.h | 3 - arch/arm/plat-omap/include/mach/omapfb.h | 4 +- arch/arm/plat-omap/include/mach/pm.h | 89 +- arch/arm/plat-omap/include/mach/prcm.h | 4 - arch/arm/plat-omap/include/mach/sdrc.h | 20 +- arch/arm/plat-omap/include/mach/serial.h | 9 - arch/arm/plat-omap/include/mach/system.h | 2 + arch/arm/plat-omap/include/mach/timex.h | 2 - arch/arm/plat-omap/mailbox.c | 2 +- arch/arm/plat-omap/mcbsp.c | 118 +- drivers/bluetooth/brf6150.c | 1 + 75 files changed, 2803 insertions(+), 7606 deletions(-) delete mode 100644 arch/arm/mach-omap2/pm-debug.c delete mode 100644 arch/arm/mach-omap2/pm.h delete mode 100644 arch/arm/mach-omap2/pm24xx.c delete mode 100644 arch/arm/mach-omap2/pm34xx.c delete mode 100644 arch/arm/mach-omap2/sleep34xx.S delete mode 100644 arch/arm/mach-omap2/smartreflex.c delete mode 100644 arch/arm/mach-omap2/smartreflex.h delete mode 100644 arch/arm/plat-omap/include/mach/board-3430sdp.h delete mode 100644 arch/arm/plat-omap/include/mach/board-omap2evm.h delete mode 100644 arch/arm/plat-omap/include/mach/board-omap3beagle.h delete mode 100644 arch/arm/plat-omap/include/mach/board-omap3evm.h create mode 100644 arch/arm/plat-omap/include/mach/clkdev.h diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index af480505dad..dafe4f71d15 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -20,64 +20,161 @@ #include #include +#include #include #include #include #include +static const struct clkops clkops_generic; +static const struct clkops clkops_uart; +static const struct clkops clkops_dspck; + #include "clock.h" +static int clk_omap1_dummy_enable(struct clk *clk) +{ + return 0; +} + +static void clk_omap1_dummy_disable(struct clk *clk) +{ +} + +static const struct clkops clkops_dummy = { + .enable = clk_omap1_dummy_enable, + .disable = clk_omap1_dummy_disable, +}; + +static struct clk dummy_ck = { + .name = "dummy", + .ops = &clkops_dummy, + .flags = RATE_FIXED, +}; + +struct omap_clk { + u32 cpu; + struct clk_lookup lk; +}; + +#define CLK(dev, con, ck, cp) \ + { \ + .cpu = cp, \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + }, \ + } + +#define CK_310 (1 << 0) +#define CK_730 (1 << 1) +#define CK_1510 (1 << 2) +#define CK_16XX (1 << 3) + +static struct omap_clk omap_clks[] = { + /* non-ULPD clocks */ + CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), + /* CK_GEN1 clocks */ + CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), + CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), + CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), + CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), + CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), + CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), + CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), + /* CK_GEN2 clocks */ + CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), + /* CK_GEN3 clocks */ + CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_730), + CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), + CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX), + CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), + CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), + CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), + CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), + CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), + CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), + CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_730), + CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), + /* ULPD clocks */ + CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), + CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), + CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), + CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), + CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), + CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), + CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), + CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), + CLK(NULL, "mclk", &mclk_16xx, CK_16XX), + CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), + CLK(NULL, "bclk", &bclk_16xx, CK_16XX), + CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), + CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), + CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), + /* Virtual clocks */ + CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), + CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310), + CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), + CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310), + CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), + CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), + CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), + CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), + CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), + CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), + CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), + CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), +}; + +static int omap1_clk_enable_generic(struct clk * clk); +static int omap1_clk_enable(struct clk *clk); +static void omap1_clk_disable_generic(struct clk * clk); +static void omap1_clk_disable(struct clk *clk); + __u32 arm_idlect1_mask; /*------------------------------------------------------------------------- * Omap1 specific clock functions *-------------------------------------------------------------------------*/ -static void omap1_watchdog_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) +static unsigned long omap1_watchdog_recalc(struct clk *clk) { - unsigned long new_rate; - - new_rate = parent_rate / 14; - - if (rate_storage == CURRENT_RATE) - clk->rate = new_rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = new_rate; + return clk->parent->rate / 14; } -static void omap1_uart_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) +static unsigned long omap1_uart_recalc(struct clk *clk) { - unsigned long new_rate; unsigned int val = __raw_readl(clk->enable_reg); - - if (val & clk->enable_bit) - new_rate = 48000000; - else - new_rate = 12000000; - - if (rate_storage == CURRENT_RATE) - clk->rate = new_rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = new_rate; + return val & clk->enable_bit ? 48000000 : 12000000; } -static void omap1_sossi_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) +static unsigned long omap1_sossi_recalc(struct clk *clk) { - unsigned long new_rate; u32 div = omap_readl(MOD_CONF_CTRL_1); div = (div >> 17) & 0x7; div++; - new_rate = clk->parent->rate / div; - if (rate_storage == CURRENT_RATE) - clk->rate = new_rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = new_rate; + return clk->parent->rate / div; } static int omap1_clk_enable_dsp_domain(struct clk *clk) @@ -101,6 +198,11 @@ static void omap1_clk_disable_dsp_domain(struct clk *clk) } } +static const struct clkops clkops_dspck = { + .enable = &omap1_clk_enable_dsp_domain, + .disable = &omap1_clk_disable_dsp_domain, +}; + static int omap1_clk_enable_uart_functional(struct clk *clk) { int ret; @@ -128,6 +230,11 @@ static void omap1_clk_disable_uart_functional(struct clk *clk) omap1_clk_disable_generic(clk); } +static const struct clkops clkops_uart = { + .enable = &omap1_clk_enable_uart_functional, + .disable = &omap1_clk_disable_uart_functional, +}; + static void omap1_clk_allow_idle(struct clk *clk) { struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; @@ -220,9 +327,6 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate) struct clk * parent; unsigned dsor_exp; - if (unlikely(!(clk->flags & RATE_CKCTL))) - return -EINVAL; - parent = clk->parent; if (unlikely(parent == NULL)) return -EIO; @@ -238,32 +342,17 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate) return dsor_exp; } -static void omap1_ckctl_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) +static unsigned long omap1_ckctl_recalc(struct clk *clk) { - int dsor; - unsigned long new_rate; - /* Calculate divisor encoded as 2-bit exponent */ - dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); + int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); - new_rate = parent_rate / dsor; - - if (unlikely(clk->rate == new_rate)) - return; /* No change, quick exit */ - - if (rate_storage == CURRENT_RATE) - clk->rate = new_rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = new_rate; + return clk->parent->rate / dsor; } -static void omap1_ckctl_recalc_dsp_domain(struct clk *clk, - unsigned long parent_rate, - u8 rate_storage) +static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) { int dsor; - unsigned long new_rate; /* Calculate divisor encoded as 2-bit exponent * @@ -276,15 +365,7 @@ static void omap1_ckctl_recalc_dsp_domain(struct clk *clk, dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); omap1_clk_disable(&api_ck.clk); - new_rate = parent_rate / dsor; - - if (unlikely(clk->rate == new_rate)) - return; /* No change, quick exit */ - - if (rate_storage == CURRENT_RATE) - clk->rate = new_rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = new_rate; + return clk->parent->rate / dsor; } /* MPU virtual clock functions */ @@ -323,32 +404,57 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate) omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); ck_dpll1.rate = ptr->pll_rate; - propagate_rate(&ck_dpll1, CURRENT_RATE); return 0; } static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) { - int ret = -EINVAL; - int dsor_exp; - __u16 regval; - - if (clk->flags & RATE_CKCTL) { - dsor_exp = calc_dsor_exp(clk, rate); - if (dsor_exp > 3) - dsor_exp = -EINVAL; - if (dsor_exp < 0) - return dsor_exp; - - regval = __raw_readw(DSP_CKCTL); - regval &= ~(3 << clk->rate_offset); - regval |= dsor_exp << clk->rate_offset; - __raw_writew(regval, DSP_CKCTL); - clk->rate = clk->parent->rate / (1 << dsor_exp); - ret = 0; - } + int dsor_exp; + u16 regval; - return ret; + dsor_exp = calc_dsor_exp(clk, rate); + if (dsor_exp > 3) + dsor_exp = -EINVAL; + if (dsor_exp < 0) + return dsor_exp; + + regval = __raw_readw(DSP_CKCTL); + regval &= ~(3 << clk->rate_offset); + regval |= dsor_exp << clk->rate_offset; + __raw_writew(regval, DSP_CKCTL); + clk->rate = clk->parent->rate / (1 << dsor_exp); + + return 0; +} + +static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) +{ + int dsor_exp = calc_dsor_exp(clk, rate); + if (dsor_exp < 0) + return dsor_exp; + if (dsor_exp > 3) + dsor_exp = 3; + return clk->parent->rate / (1 << dsor_exp); +} + +static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) +{ + int dsor_exp; + u16 regval; + + dsor_exp = calc_dsor_exp(clk, rate); + if (dsor_exp > 3) + dsor_exp = -EINVAL; + if (dsor_exp < 0) + return dsor_exp; + + regval = omap_readw(ARM_CKCTL); + regval &= ~(3 << clk->rate_offset); + regval |= dsor_exp << clk->rate_offset; + regval = verify_ckctl_value(regval); + omap_writew(regval, ARM_CKCTL); + clk->rate = clk->parent->rate / (1 << dsor_exp); + return 0; } static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) @@ -497,7 +603,7 @@ static int omap1_clk_enable(struct clk *clk) omap1_clk_deny_idle(clk->parent); } - ret = clk->enable(clk); + ret = clk->ops->enable(clk); if (unlikely(ret != 0) && clk->parent) { omap1_clk_disable(clk->parent); @@ -511,7 +617,7 @@ static int omap1_clk_enable(struct clk *clk) static void omap1_clk_disable(struct clk *clk) { if (clk->usecount > 0 && !(--clk->usecount)) { - clk->disable(clk); + clk->ops->disable(clk); if (likely(clk->parent)) { omap1_clk_disable(clk->parent); if (clk->flags & CLOCK_NO_IDLE_PARENT) @@ -525,9 +631,6 @@ static int omap1_clk_enable_generic(struct clk *clk) __u16 regval16; __u32 regval32; - if (clk->flags & ALWAYS_ENABLED) - return 0; - if (unlikely(clk->enable_reg == NULL)) { printk(KERN_ERR "clock.c: Enable for %s without enable code\n", clk->name); @@ -566,18 +669,15 @@ static void omap1_clk_disable_generic(struct clk *clk) } } +static const struct clkops clkops_generic = { + .enable = &omap1_clk_enable_generic, + .disable = &omap1_clk_disable_generic, +}; + static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) { - int dsor_exp; - - if (clk->flags & RATE_CKCTL) { - dsor_exp = calc_dsor_exp(clk, rate); - if (dsor_exp < 0) - return dsor_exp; - if (dsor_exp > 3) - dsor_exp = 3; - return clk->parent->rate / (1 << dsor_exp); - } + if (clk->flags & RATE_FIXED) + return clk->rate; if (clk->round_rate != NULL) return clk->round_rate(clk, rate); @@ -588,27 +688,9 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) { int ret = -EINVAL; - int dsor_exp; - __u16 regval; if (clk->set_rate) ret = clk->set_rate(clk, rate); - else if (clk->flags & RATE_CKCTL) { - dsor_exp = calc_dsor_exp(clk, rate); - if (dsor_exp > 3) - dsor_exp = -EINVAL; - if (dsor_exp < 0) - return dsor_exp; - - regval = omap_readw(ARM_CKCTL); - regval &= ~(3 << clk->rate_offset); - regval |= dsor_exp << clk->rate_offset; - regval = verify_ckctl_value(regval); - omap_writew(regval, ARM_CKCTL); - clk->rate = clk->parent->rate / (1 << dsor_exp); - ret = 0; - } - return ret; } @@ -651,7 +733,7 @@ static void __init omap1_clk_disable_unused(struct clk *clk) } printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); - clk->disable(clk); + clk->ops->disable(clk); printk(" done\n"); } @@ -669,10 +751,10 @@ static struct clk_functions omap1_clk_functions = { int __init omap1_clk_init(void) { - struct clk ** clkp; + struct omap_clk *c; const struct omap_clock_config *info; int crystal_type = 0; /* Default 12 MHz */ - u32 reg; + u32 reg, cpu_mask; #ifdef CONFIG_DEBUG_LL /* Resets some clocks that may be left on from bootloader, @@ -692,27 +774,24 @@ int __init omap1_clk_init(void) /* By default all idlect1 clocks are allowed to idle */ arm_idlect1_mask = ~0; - for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) { - if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) { - clk_register(*clkp); - continue; - } + for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) + clk_init_one(c->lk.clk); - if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) { - clk_register(*clkp); - continue; - } - - if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) { - clk_register(*clkp); - continue; - } - - if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) { - clk_register(*clkp); - continue; + cpu_mask = 0; + if (cpu_is_omap16xx()) + cpu_mask |= CK_16XX; + if (cpu_is_omap1510()) + cpu_mask |= CK_1510; + if (cpu_is_omap730()) + cpu_mask |= CK_730; + if (cpu_is_omap310()) + cpu_mask |= CK_310; + + for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) + if (c->cpu & cpu_mask) { + clkdev_add(&c->lk); + clk_register(c->lk.clk); } - } info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); if (info != NULL) { @@ -761,7 +840,6 @@ int __init omap1_clk_init(void) } } } - propagate_rate(&ck_dpll1, CURRENT_RATE); #else /* Find the highest supported frequency and enable it */ if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { @@ -770,11 +848,11 @@ int __init omap1_clk_init(void) omap_writew(0x2290, DPLL_CTL); omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); ck_dpll1.rate = 60000000; - propagate_rate(&ck_dpll1, CURRENT_RATE); } #endif + propagate_rate(&ck_dpll1); /* Cache rates for clocks connected to ck_ref (not dpll1) */ - propagate_rate(&ck_ref, CURRENT_RATE); + propagate_rate(&ck_ref); printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, @@ -824,4 +902,3 @@ int __init omap1_clk_init(void) return 0; } - diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 5ba55a0cbbd..17f87427125 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -13,33 +13,22 @@ #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H #define __ARCH_ARM_MACH_OMAP1_CLOCK_H -static int omap1_clk_enable_generic(struct clk * clk); -static void omap1_clk_disable_generic(struct clk * clk); -static void omap1_ckctl_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage); -static void omap1_watchdog_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage); +static unsigned long omap1_ckctl_recalc(struct clk *clk); +static unsigned long omap1_watchdog_recalc(struct clk *clk); static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); -static void omap1_sossi_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage); -static void omap1_ckctl_recalc_dsp_domain(struct clk *clk, - unsigned long parent_rate, - u8 rate_storage); -static int omap1_clk_enable_dsp_domain(struct clk * clk); +static unsigned long omap1_sossi_recalc(struct clk *clk); +static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); -static void omap1_clk_disable_dsp_domain(struct clk * clk); static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); -static void omap1_uart_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage); -static int omap1_clk_enable_uart_functional(struct clk * clk); -static void omap1_clk_disable_uart_functional(struct clk * clk); +static unsigned long omap1_uart_recalc(struct clk *clk); static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); static void omap1_init_ext_clk(struct clk * clk); static int omap1_select_table_rate(struct clk * clk, unsigned long rate); static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); -static int omap1_clk_enable(struct clk *clk); -static void omap1_clk_disable(struct clk *clk); + +static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); +static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); struct mpu_rate { unsigned long rate; @@ -158,100 +147,84 @@ static struct mpu_rate rate_table[] = { static struct clk ck_ref = { .name = "ck_ref", + .ops = &clkops_null, .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | ALWAYS_ENABLED, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk ck_dpll1 = { .name = "ck_dpll1", + .ops = &clkops_null, .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | ALWAYS_ENABLED, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct arm_idlect1_clk ck_dpll1out = { .clk = { .name = "ck_dpll1out", + .ops = &clkops_generic, .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL | - ENABLE_REG_32BIT, + .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_CKOUT_ARM, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }, .idlect_shift = 12, }; static struct clk sossi_ck = { .name = "ck_sossi", + .ops = &clkops_generic, .parent = &ck_dpll1out.clk, - .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | - ENABLE_REG_32BIT, + .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), .enable_bit = 16, .recalc = &omap1_sossi_recalc, .set_rate = &omap1_set_sossi_rate, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk arm_ck = { .name = "arm_ck", + .ops = &clkops_null, .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | RATE_CKCTL | ALWAYS_ENABLED, .rate_offset = CKCTL_ARMDIV_OFFSET, .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, }; static struct arm_idlect1_clk armper_ck = { .clk = { .name = "armper_ck", + .ops = &clkops_generic, .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | RATE_CKCTL | - CLOCK_IDLE_CONTROL, + .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_PERCK, .rate_offset = CKCTL_PERDIV_OFFSET, .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, }, .idlect_shift = 2, }; static struct clk arm_gpio_ck = { .name = "arm_gpio_ck", + .ops = &clkops_generic, .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_GPIOCK, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct arm_idlect1_clk armxor_ck = { .clk = { .name = "armxor_ck", + .ops = &clkops_generic, .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, + .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_XORPCK, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }, .idlect_shift = 1, }; @@ -259,14 +232,12 @@ static struct arm_idlect1_clk armxor_ck = { static struct arm_idlect1_clk armtim_ck = { .clk = { .name = "armtim_ck", + .ops = &clkops_generic, .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, + .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_TIMCK, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }, .idlect_shift = 9, }; @@ -274,199 +245,166 @@ static struct arm_idlect1_clk armtim_ck = { static struct arm_idlect1_clk armwdt_ck = { .clk = { .name = "armwdt_ck", + .ops = &clkops_generic, .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, + .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_WDTCK, .recalc = &omap1_watchdog_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }, .idlect_shift = 0, }; static struct clk arminth_ck16xx = { .name = "arminth_ck", + .ops = &clkops_null, .parent = &arm_ck, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, .recalc = &followparent_recalc, /* Note: On 16xx the frequency can be divided by 2 by programming * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 * * 1510 version is in TC clocks. */ - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk dsp_ck = { .name = "dsp_ck", + .ops = &clkops_generic, .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - RATE_CKCTL, .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), .enable_bit = EN_DSPCK, .rate_offset = CKCTL_DSPDIV_OFFSET, .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, }; static struct clk dspmmu_ck = { .name = "dspmmu_ck", + .ops = &clkops_null, .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - RATE_CKCTL | ALWAYS_ENABLED, .rate_offset = CKCTL_DSPMMUDIV_OFFSET, .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, }; static struct clk dspper_ck = { .name = "dspper_ck", + .ops = &clkops_dspck, .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - RATE_CKCTL, - .enable_reg = IOMEM(DSP_IDLECT2), + .enable_reg = DSP_IDLECT2, .enable_bit = EN_PERCK, .rate_offset = CKCTL_PERDIV_OFFSET, .recalc = &omap1_ckctl_recalc_dsp_domain, + .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = &omap1_clk_set_rate_dsp_domain, - .enable = &omap1_clk_enable_dsp_domain, - .disable = &omap1_clk_disable_dsp_domain, }; static struct clk dspxor_ck = { .name = "dspxor_ck", + .ops = &clkops_dspck, .parent = &ck_ref, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, - .enable_reg = IOMEM(DSP_IDLECT2), + .enable_reg = DSP_IDLECT2, .enable_bit = EN_XORPCK, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_dsp_domain, - .disable = &omap1_clk_disable_dsp_domain, }; static struct clk dsptim_ck = { .name = "dsptim_ck", + .ops = &clkops_dspck, .parent = &ck_ref, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, - .enable_reg = IOMEM(DSP_IDLECT2), + .enable_reg = DSP_IDLECT2, .enable_bit = EN_DSPTIMCK, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_dsp_domain, - .disable = &omap1_clk_disable_dsp_domain, }; /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ static struct arm_idlect1_clk tc_ck = { .clk = { .name = "tc_ck", + .ops = &clkops_null, .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | - RATE_CKCTL | - ALWAYS_ENABLED | CLOCK_IDLE_CONTROL, + .flags = CLOCK_IDLE_CONTROL, .rate_offset = CKCTL_TCDIV_OFFSET, .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, }, .idlect_shift = 6, }; static struct clk arminth_ck1510 = { .name = "arminth_ck", + .ops = &clkops_null, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | - ALWAYS_ENABLED, .recalc = &followparent_recalc, /* Note: On 1510 the frequency follows TC_CK * * 16xx version is in MPU clocks. */ - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk tipb_ck = { /* No-idle controlled by "tc_ck" */ .name = "tipb_ck", + .ops = &clkops_null, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | - ALWAYS_ENABLED, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk l3_ocpi_ck = { /* No-idle controlled by "tc_ck" */ .name = "l3_ocpi_ck", + .ops = &clkops_generic, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_OCPI_CK, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk tc1_ck = { .name = "tc1_ck", + .ops = &clkops_generic, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_TC1_CK, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk tc2_ck = { .name = "tc2_ck", + .ops = &clkops_generic, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_TC2_CK, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk dma_ck = { /* No-idle controlled by "tc_ck" */ .name = "dma_ck", + .ops = &clkops_null, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | ALWAYS_ENABLED, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk dma_lcdfree_ck = { .name = "dma_lcdfree_ck", + .ops = &clkops_null, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct arm_idlect1_clk api_ck = { .clk = { .name = "api_ck", + .ops = &clkops_generic, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, + .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_APICK, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }, .idlect_shift = 8, }; @@ -474,275 +412,238 @@ static struct arm_idlect1_clk api_ck = { static struct arm_idlect1_clk lb_ck = { .clk = { .name = "lb_ck", + .ops = &clkops_generic, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | - CLOCK_IDLE_CONTROL, + .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_LBCK, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }, .idlect_shift = 4, }; static struct clk rhea1_ck = { .name = "rhea1_ck", + .ops = &clkops_null, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk rhea2_ck = { .name = "rhea2_ck", + .ops = &clkops_null, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk lcd_ck_16xx = { .name = "lcd_ck", + .ops = &clkops_generic, .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_LCDCK, .rate_offset = CKCTL_LCDDIV_OFFSET, .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, }; static struct arm_idlect1_clk lcd_ck_1510 = { .clk = { .name = "lcd_ck", + .ops = &clkops_generic, .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | - RATE_CKCTL | CLOCK_IDLE_CONTROL, + .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_LCDCK, .rate_offset = CKCTL_LCDDIV_OFFSET, .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, }, .idlect_shift = 3, }; static struct clk uart1_1510 = { .name = "uart1_ck", + .ops = &clkops_null, /* Direct from ULPD, no real parent */ .parent = &armper_ck.clk, .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | - ENABLE_REG_32BIT | ALWAYS_ENABLED | - CLOCK_NO_IDLE_PARENT, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ .set_rate = &omap1_set_uart_rate, .recalc = &omap1_uart_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct uart_clk uart1_16xx = { .clk = { .name = "uart1_ck", + .ops = &clkops_uart, /* Direct from ULPD, no real parent */ .parent = &armper_ck.clk, .rate = 48000000, - .flags = CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT | + .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = 29, - .enable = &omap1_clk_enable_uart_functional, - .disable = &omap1_clk_disable_uart_functional, }, .sysc_addr = 0xfffb0054, }; static struct clk uart2_ck = { .name = "uart2_ck", + .ops = &clkops_null, /* Direct from ULPD, no real parent */ .parent = &armper_ck.clk, .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | ENABLE_REG_32BIT | - ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ .set_rate = &omap1_set_uart_rate, .recalc = &omap1_uart_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk uart3_1510 = { .name = "uart3_ck", + .ops = &clkops_null, /* Direct from ULPD, no real parent */ .parent = &armper_ck.clk, .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | - ENABLE_REG_32BIT | ALWAYS_ENABLED | - CLOCK_NO_IDLE_PARENT, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ .set_rate = &omap1_set_uart_rate, .recalc = &omap1_uart_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct uart_clk uart3_16xx = { .clk = { .name = "uart3_ck", + .ops = &clkops_uart, /* Direct from ULPD, no real parent */ .parent = &armper_ck.clk, .rate = 48000000, - .flags = CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT | + .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = 31, - .enable = &omap1_clk_enable_uart_functional, - .disable = &omap1_clk_disable_uart_functional, }, .sysc_addr = 0xfffb9854, }; static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ .name = "usb_clko", + .ops = &clkops_generic, /* Direct from ULPD, no parent */ .rate = 6000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | ENABLE_REG_32BIT, + .flags = RATE_FIXED | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), .enable_bit = USB_MCLK_EN_BIT, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk usb_hhc_ck1510 = { .name = "usb_hhc_ck", + .ops = &clkops_generic, /* Direct from ULPD, no parent */ .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | - ENABLE_REG_32BIT, + .flags = RATE_FIXED | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = USB_HOST_HHC_UHOST_EN, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk usb_hhc_ck16xx = { .name = "usb_hhc_ck", + .ops = &clkops_generic, /* Direct from ULPD, no parent */ .rate = 48000000, /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ - .flags = CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT, + .flags = RATE_FIXED | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ .enable_bit = 8 /* UHOST_EN */, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk usb_dc_ck = { .name = "usb_dc_ck", + .ops = &clkops_generic, /* Direct from ULPD, no parent */ .rate = 48000000, - .flags = CLOCK_IN_OMAP16XX, + .flags = RATE_FIXED, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = 4, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk mclk_1510 = { .name = "mclk", + .ops = &clkops_generic, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, + .flags = RATE_FIXED, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = 6, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk mclk_16xx = { .name = "mclk", + .ops = &clkops_generic, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .flags = CLOCK_IN_OMAP16XX, .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), .enable_bit = COM_ULPD_PLL_CLK_REQ, .set_rate = &omap1_set_ext_clk_rate, .round_rate = &omap1_round_ext_clk_rate, .init = &omap1_init_ext_clk, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk bclk_1510 = { .name = "bclk", + .ops = &clkops_generic, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, + .flags = RATE_FIXED, }; static struct clk bclk_16xx = { .name = "bclk", + .ops = &clkops_generic, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .flags = CLOCK_IN_OMAP16XX, .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), .enable_bit = SWD_ULPD_PLL_CLK_REQ, .set_rate = &omap1_set_ext_clk_rate, .round_rate = &omap1_round_ext_clk_rate, .init = &omap1_init_ext_clk, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk mmc1_ck = { .name = "mmc_ck", + .ops = &clkops_generic, /* Functional clock is direct from ULPD, interface clock is ARMPER */ .parent = &armper_ck.clk, .rate = 48000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | ENABLE_REG_32BIT | - CLOCK_NO_IDLE_PARENT, + .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = 23, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk mmc2_ck = { .name = "mmc_ck", .id = 1, + .ops = &clkops_generic, /* Functional clock is direct from ULPD, interface clock is ARMPER */ .parent = &armper_ck.clk, .rate = 48000000, - .flags = CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT | - CLOCK_NO_IDLE_PARENT, + .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = 20, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk virtual_ck_mpu = { .name = "mpu", - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + .ops = &clkops_null, .parent = &arm_ck, /* Is smarter alias for */ .recalc = &followparent_recalc, .set_rate = &omap1_select_table_rate, .round_rate = &omap1_round_to_table_rate, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK @@ -750,76 +651,19 @@ remains active during MPU idle whenever this is enabled */ static struct clk i2c_fck = { .name = "i2c_fck", .id = 1, - .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_NO_IDLE_PARENT | ALWAYS_ENABLED, + .ops = &clkops_null, + .flags = CLOCK_NO_IDLE_PARENT, .parent = &armxor_ck.clk, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, }; static struct clk i2c_ick = { .name = "i2c_ick", .id = 1, - .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | - ALWAYS_ENABLED, + .ops = &clkops_null, + .flags = CLOCK_NO_IDLE_PARENT, .parent = &armper_ck.clk, .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_generic, - .disable = &omap1_clk_disable_generic, -}; - -static struct clk * onchip_clks[] = { - /* non-ULPD clocks */ - &ck_ref, - &ck_dpll1, - /* CK_GEN1 clocks */ - &ck_dpll1out.clk, - &sossi_ck, - &arm_ck, - &armper_ck.clk, - &arm_gpio_ck, - &armxor_ck.clk, - &armtim_ck.clk, - &armwdt_ck.clk, - &arminth_ck1510, &arminth_ck16xx, - /* CK_GEN2 clocks */ - &dsp_ck, - &dspmmu_ck, - &dspper_ck, - &dspxor_ck, - &dsptim_ck, - /* CK_GEN3 clocks */ - &tc_ck.clk, - &tipb_ck, - &l3_ocpi_ck, - &tc1_ck, - &tc2_ck, - &dma_ck, - &dma_lcdfree_ck, - &api_ck.clk, - &lb_ck.clk, - &rhea1_ck, - &rhea2_ck, - &lcd_ck_16xx, - &lcd_ck_1510.clk, - /* ULPD clocks */ - &uart1_1510, - &uart1_16xx.clk, - &uart2_ck, - &uart3_1510, - &uart3_16xx.clk, - &usb_clko, - &usb_hhc_ck1510, &usb_hhc_ck16xx, - &usb_dc_ck, - &mclk_1510, &mclk_16xx, - &bclk_1510, &bclk_16xx, - &mmc1_ck, - &mmc2_ck, - /* Virtual clocks */ - &virtual_ck_mpu, - &i2c_fck, - &i2c_ick, }; #endif diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index 87539db7658..0af4d6c85b4 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c @@ -1,7 +1,7 @@ /* * Mailbox reservation modules for DSP * - * Copyright (C) 2006-2008 Nokia Corporation + * Copyright (C) 2006-2009 Nokia Corporation * Written by: Hiroshi DOYU * * This file is subject to the terms and conditions of the GNU General Public @@ -17,8 +17,6 @@ #include #include -#define DRV_NAME "omap1-mailbox" - #define MAILBOX_ARM2DSP1 0x00 #define MAILBOX_ARM2DSP1b 0x04 #define MAILBOX_DSP2ARM1 0x08 @@ -186,7 +184,7 @@ static struct platform_driver omap1_mbox_driver = { .probe = omap1_mbox_probe, .remove = __devexit_p(omap1_mbox_remove), .driver = { - .name = DRV_NAME, + .name = "omap1-mailbox", }, }; @@ -206,4 +204,4 @@ module_exit(omap1_mbox_exit); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions"); MODULE_AUTHOR("Hiroshi DOYU" ); -MODULE_ALIAS("platform:"DRV_NAME); +MODULE_ALIAS("platform:omap1-mailbox"); diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index 575ba31295c..d040c3f1027 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -28,9 +28,9 @@ #define DPS_RSTCT2_PER_EN (1 << 0) #define DSP_RSTCT2_WD_PER_EN (1 << 1) -#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) -const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" }; -#endif +static int dsp_use; +static struct clk *api_clk; +static struct clk *dsp_clk; static void omap1_mcbsp_request(unsigned int id) { @@ -39,20 +39,40 @@ static void omap1_mcbsp_request(unsigned int id) * are DSP public peripherals. */ if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { - omap_dsp_request_mem(); - /* - * DSP external peripheral reset - * FIXME: This should be moved to dsp code - */ - __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN | - DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2); + if (dsp_use++ == 0) { + api_clk = clk_get(NULL, "api_clk"); + dsp_clk = clk_get(NULL, "dsp_clk"); + if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) { + clk_enable(api_clk); + clk_enable(dsp_clk); + + omap_dsp_request_mem(); + /* + * DSP external peripheral reset + * FIXME: This should be moved to dsp code + */ + __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN | + DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2); + } + } } } static void omap1_mcbsp_free(unsigned int id) { - if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) - omap_dsp_release_mem(); + if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { + if (--dsp_use == 0) { + omap_dsp_release_mem(); + if (!IS_ERR(api_clk)) { + clk_disable(api_clk); + clk_put(api_clk); + } + if (!IS_ERR(dsp_clk)) { + clk_disable(dsp_clk); + clk_put(dsp_clk); + } + } + } } static struct omap_mcbsp_ops omap1_mcbsp_ops = { @@ -94,8 +114,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { .rx_irq = INT_McBSP1RX, .tx_irq = INT_McBSP1TX, .ops = &omap1_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 3, }, { .phys_base = OMAP1510_MCBSP2_BASE, @@ -112,8 +130,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { .rx_irq = INT_McBSP3RX, .tx_irq = INT_McBSP3TX, .ops = &omap1_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 3, }, }; #define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) @@ -131,8 +147,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { .rx_irq = INT_McBSP1RX, .tx_irq = INT_McBSP1TX, .ops = &omap1_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 3, }, { .phys_base = OMAP1610_MCBSP2_BASE, @@ -149,8 +163,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { .rx_irq = INT_McBSP3RX, .tx_irq = INT_McBSP3TX, .ops = &omap1_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 3, }, }; #define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index c95332bf30c..76acefa0c76 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -21,15 +21,9 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # Power Management ifeq ($(CONFIG_PM),y) obj-y += pm.o -obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o -obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o -obj-$(CONFIG_PM_DEBUG) += pm-debug.o endif -# SmartReflex driver -obj-$(CONFIG_OMAP_SMARTREFLEX) += smartreflex.o - # Clock framework obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o diff --git a/arch/arm/mach-omap2/board-3430sdp-flash.c b/arch/arm/mach-omap2/board-3430sdp-flash.c index 51dd839c61b..f0e25a46417 100644 --- a/arch/arm/mach-omap2/board-3430sdp-flash.c +++ b/arch/arm/mach-omap2/board-3430sdp-flash.c @@ -28,6 +28,27 @@ #define NAND_BLOCK_SIZE SZ_128K +/* NAND */ +/* IMPORTANT NOTE ON MAPPING + * 3430SDP - 34XX + * ---------- + * NOR always on 0x04000000 for SDPV1 + * NOR always on 0x10000000 for SDPV2 + * MPDB always on 0x08000000 + * NAND always on 0x0C000000 + * OneNand Mapped to 0x20000000 + * Boot Mode(NAND/NOR). The other on CS1 + */ +#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (64 Meg aligned) */ +#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (256 Meg aligned) */ +#define DEBUG_BASE 0x08000000 /* debug board */ +#define NAND_BASE 0x0C000000 /* NAND flash */ +#define ONENAND_MAP 0x20000000 /* OneNand flash */ + +/* various memory sizes */ +#define FLASH_SIZE_SDPV1 SZ_64M +#define FLASH_SIZE_SDPV2 SZ_128M + static struct mtd_partition sdp_nor_partitions[] = { /* bootloader (U-Boot, etc) in first sector */ { diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 0a1099ead14..03acac79adf 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -61,6 +61,8 @@ #define TWL4030_MSECURE_GPIO 22 +extern void sdp3430_flash_init(void); + static struct resource sdp3430_smc91x_resources[] = { [0] = { .flags = IORESOURCE_MEM, diff --git a/arch/arm/mach-omap2/board-n800-usb.c b/arch/arm/mach-omap2/board-n800-usb.c index e182a93ad19..8250014bee6 100644 --- a/arch/arm/mach-omap2/board-n800-usb.c +++ b/arch/arm/mach-omap2/board-n800-usb.c @@ -129,7 +129,7 @@ static int tusb_set_clock(struct clk *osc_ck, int state) if (osc_ck_on > 0) return -ENODEV; - omap2_block_sleep(); + //omap2_block_sleep(); clk_enable(osc_ck); osc_ck_on = 1; } else { @@ -138,7 +138,7 @@ static int tusb_set_clock(struct clk *osc_ck, int state) clk_disable(osc_ck); osc_ck_on = 0; - omap2_allow_sleep(); + //omap2_allow_sleep(); } return 0; diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c index cb32b61c667..f1552f0d7b6 100644 --- a/arch/arm/mach-omap2/board-n800.c +++ b/arch/arm/mach-omap2/board-n800.c @@ -41,6 +41,7 @@ #include #include #include +#include #include <../drivers/cbus/tahvo.h> #include <../drivers/media/video/tcm825x.h> diff --git a/arch/arm/mach-omap2/board-omap2evm.c b/arch/arm/mach-omap2/board-omap2evm.c index 5ec38e25358..86477ccc996 100644 --- a/arch/arm/mach-omap2/board-omap2evm.c +++ b/arch/arm/mach-omap2/board-omap2evm.c @@ -42,8 +42,12 @@ #include "mmc-twl4030.h" +#define OMAP2EVM_ETHR_START 0x2c000000 +#define OMAP2EVM_ETHR_SIZE 1024 +#define OMAP2EVM_ETHR_GPIO_IRQ 149 +#define OMAP2_EVM_TS_GPIO 85 -#define GPMC_OFF_CONFIG1_0 0x60 +#define GPMC_OFF_CONFIG1_0 0x60 static struct mtd_partition omap2evm_nand_partitions[] = { { diff --git a/arch/arm/mach-omap2/board-omap3evm-flash.c b/arch/arm/mach-omap2/board-omap3evm-flash.c index 8d96e35b91f..b58b7c6b1af 100644 --- a/arch/arm/mach-omap2/board-omap3evm-flash.c +++ b/arch/arm/mach-omap2/board-omap3evm-flash.c @@ -23,6 +23,8 @@ #include #include +#define ONENAND_MAP 0x20000000 + static int omap3evm_onenand_setup(void __iomem *, int freq); static struct mtd_partition omap3evm_onenand_partitions[] = { diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 024d7c4a409..6eb3c523091 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -41,6 +41,14 @@ #include "twl4030-generic-scripts.h" #include "mmc-twl4030.h" +#define OMAP3_EVM_TS_GPIO 175 + +#define OMAP3EVM_ETHR_START 0x2c000000 +#define OMAP3EVM_ETHR_SIZE 1024 +#define OMAP3EVM_ETHR_GPIO_IRQ 176 +#define OMAP3EVM_SMC911X_CS 5 + +extern void omap3evm_flash_init(void); static struct resource omap3evm_smc911x_resources[] = { [0] = { diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 9b70adae366..f9cc015d36d 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -60,6 +60,9 @@ #define GPMC_CS0_BASE 0x60 #define GPMC_CS_SIZE 0x30 +#define OVERO_SMSC911X_CS 5 +#define OVERO_SMSC911X_GPIO 176 + #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #include diff --git a/arch/arm/mach-omap2/board-rx51-flash.c b/arch/arm/mach-omap2/board-rx51-flash.c index fe9329d2c09..f3b7eaf5d8d 100644 --- a/arch/arm/mach-omap2/board-rx51-flash.c +++ b/arch/arm/mach-omap2/board-rx51-flash.c @@ -10,6 +10,7 @@ #include #include +#include extern void __init n800_flash_init(void); diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index c90120ca63d..768f507a569 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -31,6 +31,7 @@ #include #include #include +#include static struct omap_uart_config rx51_uart_config = { .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 41662fdea1d..4247a153441 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -26,10 +26,7 @@ #include #include -#include #include -#include -#include #include #include @@ -71,55 +68,12 @@ #define DPLL_FINT_UNDERFLOW -1 #define DPLL_FINT_INVALID -2 -/* Bitmask to isolate the register type of clk.enable_reg */ -#define PRCM_REGTYPE_MASK 0xf0 -/* various CM register type options */ -#define CM_FCLKEN_REGTYPE 0x00 -#define CM_ICLKEN_REGTYPE 0x10 -#define CM_IDLEST_REGTYPE 0x20 - u8 cpu_mask; /*------------------------------------------------------------------------- * OMAP2/3 specific clock functions *-------------------------------------------------------------------------*/ -/* - * _omap2_clk_read_reg - read a clock register - * @clk: struct clk * - * - * Given a struct clk *, returns the value of the clock's register. - */ -static u32 _omap2_clk_read_reg(u16 reg_offset, struct clk *clk) -{ - if (clk->prcm_mod & CLK_REG_IN_SCM) - return omap_ctrl_readl(reg_offset); - else if (clk->prcm_mod & CLK_REG_IN_PRM) - return prm_read_mod_reg(clk->prcm_mod & PRCM_MOD_ADDR_MASK, - reg_offset); - else - return cm_read_mod_reg(clk->prcm_mod, reg_offset); -} - -/* - * _omap2_clk_write_reg - write a clock's register - * @v: value to write to the clock's enable_reg - * @clk: struct clk * - * - * Given a register value @v and struct clk * @clk, writes the value of @v to - * the clock's enable register. No return value. - */ -static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk) -{ - if (clk->prcm_mod & CLK_REG_IN_SCM) - omap_ctrl_writel(v, reg_offset); - else if (clk->prcm_mod & CLK_REG_IN_PRM) - prm_write_mod_reg(v, clk->prcm_mod & PRCM_MOD_ADDR_MASK, - reg_offset); - else - cm_write_mod_reg(v, clk->prcm_mod, reg_offset); -} - /** * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware * @clk: struct clk * @@ -137,7 +91,7 @@ static void _omap2xxx_clk_commit(struct clk *clk) return; prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, - OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); + OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); /* OCP barrier */ prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); } @@ -200,14 +154,17 @@ void omap2_init_clk_clkdm(struct clk *clk) { struct clockdomain *clkdm; - clkdm = clkdm_lookup(clk->clkdm.name); + if (!clk->clkdm_name) + return; + + clkdm = clkdm_lookup(clk->clkdm_name); if (clkdm) { pr_debug("clock: associated clk %s to clkdm %s\n", - clk->name, clk->clkdm.name); - clk->clkdm.ptr = clkdm; + clk->name, clk->clkdm_name); + clk->clkdm = clkdm; } else { - pr_err("clock: %s: could not associate to clkdm %s\n", - clk->name, clk->clkdm.name); + pr_debug("clock: could not associate clk %s to " + "clkdm %s\n", clk->name, clk->clkdm_name); } } @@ -228,8 +185,7 @@ void omap2_init_clksel_parent(struct clk *clk) if (!clk->clksel) return; - r = _omap2_clk_read_reg(clk->clksel_reg, clk); - r &= clk->clksel_mask; + r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; r >>= __ffs(clk->clksel_mask); for (clks = clk->clksel; clks->parent && !found; clks++) { @@ -241,11 +197,7 @@ void omap2_init_clksel_parent(struct clk *clk) clk->name, clks->parent->name, ((clk->parent) ? clk->parent->name : "NULL")); - if (clk->parent) - omap_clk_del_child(clk->parent, - clk); - clk->parent = clks->parent; - omap_clk_add_child(clk->parent, clk); + clk_reparent(clk, clks->parent); }; found = 1; } @@ -262,7 +214,6 @@ void omap2_init_clksel_parent(struct clk *clk) /** * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate * @clk: struct clk * of a DPLL - * @parent_rate: rate of the parent of the DPLL clock * * DPLLs can be locked or bypassed - basically, enabled or disabled. * When locked, the DPLL output depends on the M and N values. When @@ -274,7 +225,7 @@ void omap2_init_clksel_parent(struct clk *clk) * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 * if the clock @clk is not a DPLL. */ -u32 omap2_get_dpll_rate(struct clk *clk, unsigned long parent_rate) +u32 omap2_get_dpll_rate(struct clk *clk) { long long dpll_clk; u32 dpll_mult, dpll_div, v; @@ -285,31 +236,27 @@ u32 omap2_get_dpll_rate(struct clk *clk, unsigned long parent_rate) return 0; /* Return bypass rate if DPLL is bypassed */ - v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg); + v = __raw_readl(dd->control_reg); v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) - return parent_rate; - + return dd->clk_bypass->rate; } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) - return dd->bypass_clk->rate; - + return dd->clk_bypass->rate; } - v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg); + v = __raw_readl(dd->mult_div1_reg); dpll_mult = v & dd->mult_mask; dpll_mult >>= __ffs(dd->mult_mask); dpll_div = v & dd->div1_mask; dpll_div >>= __ffs(dd->div1_mask); - dpll_clk = (long long)parent_rate * dpll_mult; + dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; do_div(dpll_clk, dpll_div + 1); return dpll_clk; @@ -319,35 +266,26 @@ u32 omap2_get_dpll_rate(struct clk *clk, unsigned long parent_rate) * Used for clocks that have the same value as the parent clock, * divided by some factor */ -void omap2_fixed_divisor_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) +unsigned long omap2_fixed_divisor_recalc(struct clk *clk) { - unsigned long rate; - - WARN_ON(!clk->fixed_div); /* XXX move this to init */ + WARN_ON(!clk->fixed_div); - rate = parent_rate / clk->fixed_div; - - if (rate_storage == CURRENT_RATE) - clk->rate = rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = rate; + return clk->parent->rate / clk->fixed_div; } /** * omap2_wait_clock_ready - wait for clock to enable - * @prcm_mod: CM submodule offset from CM_BASE (e.g., "MPU_MOD") - * @reg_index: offset of CM register address from prcm_mod + * @reg: physical address of clock IDLEST register * @mask: value to mask against to determine if the clock is active * @name: name of the clock (for printk) * * Returns 1 if the clock enabled in time, or 0 if it failed to enable * in roughly MAX_CLOCK_ENABLE_WAIT microseconds. */ -int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask, - const char *name) +int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) { - int i = 0, ena = 0; + int i = 0; + int ena = 0; /* * 24xx uses 0 to indicate not ready, and 1 to indicate ready. @@ -359,7 +297,7 @@ int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask, ena = 0; /* Wait for lock */ - while (((cm_read_mod_reg(prcm_mod, reg_index) & mask) != ena) && + while (((__raw_readl(reg) & mask) != ena) && (i++ < MAX_CLOCK_ENABLE_WAIT)) { udelay(1); } @@ -370,147 +308,167 @@ int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask, printk(KERN_ERR "Clock %s didn't enable in %d tries\n", name, MAX_CLOCK_ENABLE_WAIT); + return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0; }; /* - * omap2_clk_wait_ready - wait for a OMAP module to come out of target idle - * @clk: struct clk * recently enabled to indicate the module to test - * - * Wait for an OMAP module with a target idle state bit to come out of - * idle once both its interface clock and primary functional clock are - * both enabled. Any register read or write to the device before it - * returns from idle will cause an abort. Not all modules have target - * idle state bits (for example, DSS and CAM on OMAP24xx); so we don't - * wait for those. No return value. - * - * We don't need special code here for INVERT_ENABLE for the time - * being since INVERT_ENABLE only applies to clocks enabled by - * CM_CLKEN_PLL. - * - * REVISIT: This function is misnamed: it should be something like - * "omap2_module_wait_ready", and in the long-term, it does not belong - * in the clock framework. It also shouldn't be doing register - * arithmetic to determine the companion clock. + * Note: We don't need special code here for INVERT_ENABLE + * for the time being since INVERT_ENABLE only applies to clocks enabled by + * CM_CLKEN_PLL */ static void omap2_clk_wait_ready(struct clk *clk) { - u16 other_reg, idlest_reg; - u32 other_bit; - - if (!(clk->flags & WAIT_READY)) - return; + void __iomem *reg, *other_reg, *st_reg; + u32 bit; - /* If we are enabling an iclk, also test the fclk; and vice versa */ - other_bit = 1 << clk->enable_bit; - other_reg = clk->enable_reg & ~PRCM_REGTYPE_MASK; + /* + * REVISIT: This code is pretty ugly. It would be nice to generalize + * it and pull it into struct clk itself somehow. + */ + reg = clk->enable_reg; - if (clk->enable_reg & CM_ICLKEN_REGTYPE) - other_reg |= CM_FCLKEN_REGTYPE; - else - other_reg |= CM_ICLKEN_REGTYPE; + /* + * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes + * it's just a matter of XORing the bits. + */ + other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN)); - /* Ensure functional and interface clocks are running. */ - if (!(cm_read_mod_reg(clk->prcm_mod, other_reg) & other_bit)) + /* Check if both functional and interface clocks + * are running. */ + bit = 1 << clk->enable_bit; + if (!(__raw_readl(other_reg) & bit)) return; + st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */ - idlest_reg = other_reg & ~PRCM_REGTYPE_MASK; - idlest_reg |= CM_IDLEST_REGTYPE; - - omap2_wait_clock_ready(clk->prcm_mod, idlest_reg, 1 << clk->idlest_bit, - clk->name); + omap2_wait_clock_ready(st_reg, bit, clk->name); } -/* Enables clock without considering parent dependencies or use count - * REVISIT: Maybe change this to use clk->enable like on omap1? - */ -static int _omap2_clk_enable(struct clk *clk) +static int omap2_dflt_clk_enable(struct clk *clk) { u32 v; - if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) - return 0; - - if (clk->enable) - return clk->enable(clk); + if (unlikely(clk->enable_reg == NULL)) { + printk(KERN_ERR "clock.c: Enable for %s without enable code\n", + clk->name); + return 0; /* REVISIT: -EINVAL */ + } - v = _omap2_clk_read_reg(clk->enable_reg, clk); + v = __raw_readl(clk->enable_reg); if (clk->flags & INVERT_ENABLE) v &= ~(1 << clk->enable_bit); else v |= (1 << clk->enable_bit); - _omap2_clk_write_reg(v, clk->enable_reg, clk); - v = _omap2_clk_read_reg(clk->enable_reg, clk); /* OCP barrier */ - - omap2_clk_wait_ready(clk); + __raw_writel(v, clk->enable_reg); + v = __raw_readl(clk->enable_reg); /* OCP barrier */ return 0; } -/* Disables clock without considering parent dependencies or use count */ -static void _omap2_clk_disable(struct clk *clk) +static int omap2_dflt_clk_enable_wait(struct clk *clk) { - u32 v; + int ret; - if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) - return; + if (!clk->enable_reg) { + printk(KERN_ERR "clock.c: Enable for %s without enable code\n", + clk->name); + return 0; /* REVISIT: -EINVAL */ + } + + ret = omap2_dflt_clk_enable(clk); + if (ret == 0) + omap2_clk_wait_ready(clk); + return ret; +} + +static void omap2_dflt_clk_disable(struct clk *clk) +{ + u32 v; - if (clk->disable) { - clk->disable(clk); + if (!clk->enable_reg) { + /* + * 'Independent' here refers to a clock which is not + * controlled by its parent. + */ + printk(KERN_ERR "clock: clk_disable called on independent " + "clock %s which has no enable_reg\n", clk->name); return; } - v = _omap2_clk_read_reg(clk->enable_reg, clk); + v = __raw_readl(clk->enable_reg); if (clk->flags & INVERT_ENABLE) v |= (1 << clk->enable_bit); else v &= ~(1 << clk->enable_bit); - _omap2_clk_write_reg(v, clk->enable_reg, clk); + __raw_writel(v, clk->enable_reg); /* No OCP barrier needed here since it is a disable operation */ } +const struct clkops clkops_omap2_dflt_wait = { + .enable = omap2_dflt_clk_enable_wait, + .disable = omap2_dflt_clk_disable, +}; + +const struct clkops clkops_omap2_dflt = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, +}; + +/* Enables clock without considering parent dependencies or use count + * REVISIT: Maybe change this to use clk->enable like on omap1? + */ +static int _omap2_clk_enable(struct clk *clk) +{ + return clk->ops->enable(clk); +} + +/* Disables clock without considering parent dependencies or use count */ +static void _omap2_clk_disable(struct clk *clk) +{ + clk->ops->disable(clk); +} + void omap2_clk_disable(struct clk *clk) { if (clk->usecount > 0 && !(--clk->usecount)) { _omap2_clk_disable(clk); if (clk->parent) omap2_clk_disable(clk->parent); - omap2_clkdm_clk_disable(clk->clkdm.ptr, clk); + if (clk->clkdm) + omap2_clkdm_clk_disable(clk->clkdm, clk); } } int omap2_clk_enable(struct clk *clk) { - int ret; - - if (++clk->usecount > 1) - return 0; - - omap2_clkdm_clk_enable(clk->clkdm.ptr, clk); - - if (clk->parent) { - int parent_ret; + int ret = 0; - parent_ret = omap2_clk_enable(clk->parent); + if (clk->usecount++ == 0) { + if (clk->clkdm) + omap2_clkdm_clk_enable(clk->clkdm, clk); - if (parent_ret != 0) { - clk->usecount--; - omap2_clkdm_clk_disable(clk->clkdm.ptr, clk); - return parent_ret; + if (clk->parent) { + ret = omap2_clk_enable(clk->parent); + if (ret) + goto err; } - } - ret = _omap2_clk_enable(clk); + ret = _omap2_clk_enable(clk); + if (ret) { + if (clk->parent) + omap2_clk_disable(clk->parent); - if (ret != 0) { - clk->usecount--; - omap2_clkdm_clk_disable(clk->clkdm.ptr, clk); - if (clk->parent) - omap2_clk_disable(clk->parent); + goto err; + } } + return ret; +err: + if (clk->clkdm) + omap2_clkdm_clk_disable(clk->clkdm, clk); + clk->usecount--; return ret; } @@ -518,26 +476,22 @@ int omap2_clk_enable(struct clk *clk) * Used for clocks that are part of CLKSEL_xyz governed clocks. * REVISIT: Maybe change to use clk->enable() functions like on omap1? */ -void omap2_clksel_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) +unsigned long omap2_clksel_recalc(struct clk *clk) { - u32 div = 0; unsigned long rate; + u32 div = 0; pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); div = omap2_clksel_get_divisor(clk); if (div == 0) - return; + return clk->rate; - rate = parent_rate / div; + rate = clk->parent->rate / div; - if (rate_storage == CURRENT_RATE) - clk->rate = rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = rate; + pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); - pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); + return rate; } /** @@ -580,6 +534,8 @@ static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, * * Finds 'best' divider value in an array based on the source and target * rates. The divider array must be sorted with smallest divider first. + * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, + * they are only settable as part of virtual_prcm set. * * Returns the rounded clock rate or returns 0xffffffff on error. */ @@ -640,6 +596,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, * Compatibility wrapper for OMAP clock framework * Finds best target rate based on the source clock and possible dividers. * rates. The divider array must be sorted with smallest divider first. + * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, + * they are only settable as part of virtual_prcm set. * * Returns the rounded clock rate or returns 0xffffffff on error. */ @@ -654,9 +612,13 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) /* Given a clock and a rate apply a clock specific rounding function */ long omap2_clk_round_rate(struct clk *clk, unsigned long rate) { - if (clk->round_rate != NULL) + if (clk->round_rate) return clk->round_rate(clk, rate); + if (clk->flags & RATE_FIXED) + printk(KERN_ERR "clock: generic omap2_clk_round_rate called " + "on fixed-rate clock %s\n", clk->name); + return clk->rate; } @@ -743,8 +705,7 @@ u32 omap2_clksel_get_divisor(struct clk *clk) if (!clk->clksel_mask) return 0; - v = _omap2_clk_read_reg(clk->clksel_reg, clk); - v &= clk->clksel_mask; + v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; v >>= __ffs(clk->clksel_mask); return omap2_clksel_to_divisor(clk, v); @@ -759,17 +720,17 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); if (validrate != rate) - return -EINVAL; + return -EINVAL; field_val = omap2_divisor_to_clksel(clk, new_div); if (field_val == ~0) return -EINVAL; - v = _omap2_clk_read_reg(clk->clksel_reg, clk); + v = __raw_readl(clk->clksel_reg); v &= ~clk->clksel_mask; v |= field_val << __ffs(clk->clksel_mask); - _omap2_clk_write_reg(v, clk->clksel_reg, clk); - v = _omap2_clk_read_reg(clk->clksel_reg, clk); /* OCP barrier */ + __raw_writel(v, clk->clksel_reg); + v = __raw_readl(clk->clksel_reg); /* OCP barrier */ clk->rate = clk->parent->rate / new_div; @@ -786,7 +747,13 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); - if (clk->set_rate != NULL) + /* CONFIG_PARTICIPANT clocks are changed only in sets via the + rate table mechanism, driven by mpu_speed */ + if (clk->flags & CONFIG_PARTICIPANT) + return -EINVAL; + + /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ + if (clk->set_rate) ret = clk->set_rate(clk, rate); return ret; @@ -830,6 +797,9 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) { u32 field_val, v, parent_div; + if (clk->flags & CONFIG_PARTICIPANT) + return -EINVAL; + if (!clk->clksel) return -EINVAL; @@ -837,22 +807,16 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) if (!parent_div) return -EINVAL; - if (clk->usecount > 0) - omap2_clk_disable(clk); - /* Set new source value (previous dividers if any in effect) */ - v = _omap2_clk_read_reg(clk->clksel_reg, clk); + v = __raw_readl(clk->clksel_reg); v &= ~clk->clksel_mask; v |= field_val << __ffs(clk->clksel_mask); - _omap2_clk_write_reg(v, clk->clksel_reg, clk); - v = _omap2_clk_read_reg(clk->clksel_reg, clk); /* OCP barrier */ + __raw_writel(v, clk->clksel_reg); + v = __raw_readl(clk->clksel_reg); /* OCP barrier */ _omap2xxx_clk_commit(clk); - clk->parent = new_parent; - - if (clk->usecount > 0) - omap2_clk_enable(clk); + clk_reparent(clk, new_parent); /* CLKSEL clocks follow their parents' rates, divided by a divisor */ clk->rate = new_parent->rate; @@ -866,11 +830,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) return 0; } -struct clk *omap2_clk_get_parent(struct clk *clk) -{ - return clk->parent; -} - /* DPLL rate rounding code */ /** @@ -992,7 +951,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) pr_debug("clock: starting DPLL round_rate for clock %s, target rate " "%ld\n", clk->name, target_rate); - scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR); + scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; dd->last_rounded_rate = 0; @@ -1019,7 +978,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) break; r = _dpll_test_mult(&m, n, &new_rate, target_rate, - clk->parent->rate); + dd->clk_ref->rate); /* m can't be set low enough for this n - try with a larger n */ if (r == DPLL_MULT_UNDERFLOW) @@ -1050,7 +1009,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) dd->last_rounded_m = min_e_m; dd->last_rounded_n = min_e_n; - dd->last_rounded_rate = _dpll_compute_new_rate(clk->parent->rate, + dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, min_e_m, min_e_n); pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", @@ -1072,7 +1031,7 @@ void omap2_clk_disable_unused(struct clk *clk) v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; - regval32 = _omap2_clk_read_reg(clk->enable_reg, clk); + regval32 = __raw_readl(clk->enable_reg); if ((regval32 & (1 << clk->enable_bit)) == v) return; @@ -1084,15 +1043,3 @@ void omap2_clk_disable_unused(struct clk *clk) _omap2_clk_disable(clk); } #endif - -int omap2_clk_register(struct clk *clk) -{ - if (!clk->clkdm.name) { - pr_debug("clock: %s: missing clockdomain", clk->name); - WARN_ON(1); - return -EINVAL; - } - - omap2_init_clk_clkdm(clk); - return 0; -} diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index f4d489f4cd1..2679ddfa642 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -37,7 +37,6 @@ #define OMAP3XXX_EN_DPLL_LOCKED 0x7 int omap2_clk_init(void); -int omap2_clk_register(struct clk *clk); int omap2_clk_enable(struct clk *clk); void omap2_clk_disable(struct clk *clk); long omap2_clk_round_rate(struct clk *clk, unsigned long rate); @@ -45,7 +44,6 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); -struct clk *omap2_clk_get_parent(struct clk *clk); #ifdef CONFIG_OMAP_RESET_CLOCKS void omap2_clk_disable_unused(struct clk *clk); @@ -53,8 +51,7 @@ void omap2_clk_disable_unused(struct clk *clk); #define omap2_clk_disable_unused NULL #endif -void omap2_clksel_recalc(struct clk *clk, unsigned long new_parent_rate, - u8 rate_storage); +unsigned long omap2_clksel_recalc(struct clk *clk); void omap2_init_clk_clkdm(struct clk *clk); void omap2_init_clksel_parent(struct clk *clk); u32 omap2_clksel_get_divisor(struct clk *clk); @@ -62,15 +59,16 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, u32 *new_div); u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); -void omap2_fixed_divisor_recalc(struct clk *clk, unsigned long new_parent_rate, - u8 rate_storage); +unsigned long omap2_fixed_divisor_recalc(struct clk *clk); long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); -u32 omap2_get_dpll_rate(struct clk *clk, unsigned long parent_rate); -int omap2_wait_clock_ready(s16 prcm_mod, u16 idlest_reg, u32 cval, - const char *name); +u32 omap2_get_dpll_rate(struct clk *clk); +int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); void omap2_clk_prepare_for_reboot(void); +extern const struct clkops clkops_omap2_dflt_wait; +extern const struct clkops clkops_omap2_dflt; + extern u8 cpu_mask; /* clksel_rate data common to 24xx/343x */ diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index 53864c09270..1e839c5a28c 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -28,19 +28,195 @@ #include #include -#include #include #include #include +#include #include #include "clock.h" -#include "clock24xx.h" #include "prm.h" #include "prm-regbits-24xx.h" #include "cm.h" #include "cm-regbits-24xx.h" +static const struct clkops clkops_oscck; +static const struct clkops clkops_fixed; + +#include "clock24xx.h" + +struct omap_clk { + u32 cpu; + struct clk_lookup lk; +}; + +#define CLK(dev, con, ck, cp) \ + { \ + .cpu = cp, \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + }, \ + } + +#define CK_243X (1 << 0) +#define CK_242X (1 << 1) + +static struct omap_clk omap24xx_clks[] = { + /* external root sources */ + CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), + CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), + CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), + CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), + /* internal analog sources */ + CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X), + CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X), + CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X), + /* internal prcm root sources */ + CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X), + CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X), + CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X), + CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X), + CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X), + CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X), + CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X), + CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X), + CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), + CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), + CLK(NULL, "emul_ck", &emul_ck, CK_242X), + /* mpu domain clocks */ + CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X), + /* dsp domain clocks */ + CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X), + CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X), + CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), + CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), + CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), + CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), + /* GFX domain clocks */ + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X), + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X), + CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X), + /* Modem domain clocks */ + CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), + CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), + /* DSS domain clocks */ + CLK(NULL, "dss_ick", &dss_ick, CK_243X | CK_242X), + CLK(NULL, "dss1_fck", &dss1_fck, CK_243X | CK_242X), + CLK(NULL, "dss2_fck", &dss2_fck, CK_243X | CK_242X), + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X | CK_242X), + /* L3 domain clocks */ + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X), + /* L4 domain clocks */ + CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X), + /* virtual meta-group clock */ + CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X), + /* general l4 interface ck, multi-parent functional clk */ + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X), + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X), + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X), + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X), + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X), + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X), + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X), + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X), + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X), + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X), + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X), + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X), + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X), + CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X), + CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X), + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), + CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), + CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), + CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X), + CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X), + CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X), + CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), + CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), + CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X), + CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X), + CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X), + CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X), + CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X), + CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X), + CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X), + CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X), + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X), + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X), + CLK(NULL, "icr_ick", &icr_ick, CK_243X), + CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X), + CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X), + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X), + CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X), + CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X), + CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), + CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X), + CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X), + CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), + CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), + CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X), + CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X), + CLK(NULL, "eac_ick", &eac_ick, CK_242X), + CLK(NULL, "eac_fck", &eac_fck, CK_242X), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X), + CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X), + CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X), + CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), + CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), + CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X), + CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), + CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X), + CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X), + CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X), + CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), + CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), + CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X), + CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X), + CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X), + CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), + CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), + CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), + CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), + CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), + CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), + CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), + CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), + CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), + CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), + CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), + CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), +}; + /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ #define EN_APLL_STOPPED 0 #define EN_APLL_LOCKED 3 @@ -63,7 +239,6 @@ static struct clk *sclk; /** * omap2xxx_clk_get_core_rate - return the CORE_CLK rate * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") - * @parent_rate: rate of the parent of the dpll_ck * * Returns the CORE_CLK rate. CORE_CLK can have one of three rate * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz @@ -71,13 +246,12 @@ static struct clk *sclk; * struct clk *dpll_ck, which is a composite clock of dpll_ck and * core_ck. */ -static u32 omap2xxx_clk_get_core_rate(struct clk *clk, - unsigned long parent_rate) +static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) { long long core_clk; u32 v; - core_clk = omap2_get_dpll_rate(clk, parent_rate); + core_clk = omap2_get_dpll_rate(clk); v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); v &= OMAP24XX_CORE_CLK_SRC_MASK; @@ -90,43 +264,44 @@ static u32 omap2xxx_clk_get_core_rate(struct clk *clk, return core_clk; } -static unsigned long omap2xxx_clk_find_oppset_by_mpurate(unsigned long mpu_speed, - struct prcm_config **prcm) +static int omap2_enable_osc_ck(struct clk *clk) { - unsigned long found_speed = 0; - struct prcm_config *p; + u32 pcc; - p = *prcm; + pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); - for (p = rate_table; p->mpu_speed; p++) { - if (!(p->flags & cpu_mask)) - continue; + __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, + OMAP24XX_PRCM_CLKSRC_CTRL); - if (p->xtal_speed != sys_ck.rate) - continue; - - if (p->mpu_speed <= mpu_speed) { - found_speed = p->mpu_speed; - break; - } - } - - return found_speed; + return 0; } -static int omap2_enable_osc_ck(struct clk *clk) +static void omap2_disable_osc_ck(struct clk *clk) { - prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 0, - OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET); + u32 pcc; - return 0; + pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); + + __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, + OMAP24XX_PRCM_CLKSRC_CTRL); } -static void omap2_disable_osc_ck(struct clk *clk) +static const struct clkops clkops_oscck = { + .enable = &omap2_enable_osc_ck, + .disable = &omap2_disable_osc_ck, +}; + +#ifdef OLD_CK +/* Recalculate SYST_CLK */ +static void omap2_sys_clk_recalc(struct clk * clk) { - prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK, - OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET); + u32 div = PRCM_CLKSRC_CTRL; + div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ + div >>= clk->rate_offset; + clk->rate = (clk->parent->rate / div); + propagate_rate(clk); } +#endif /* OLD_CK */ /* Enable an APLL if off */ static int omap2_clk_fixed_enable(struct clk *clk) @@ -149,7 +324,8 @@ static int omap2_clk_fixed_enable(struct clk *clk) else if (clk == &apll54_ck) cval = OMAP24XX_ST_54M_APLL; - omap2_wait_clock_ready(PLL_MOD, CM_IDLEST, cval, clk->name); + omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval, + clk->name); /* * REVISIT: Should we return an error code if omap2_wait_clock_ready() @@ -168,6 +344,11 @@ static void omap2_clk_fixed_disable(struct clk *clk) cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); } +static const struct clkops clkops_fixed = { + .enable = &omap2_clk_fixed_enable, + .disable = &omap2_clk_fixed_disable, +}; + /* * Uses the current prcm set to tell if a rate is valid. * You can go slower, but not faster within a given rate set. @@ -201,17 +382,9 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) } -static void omap2_dpllcore_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) +static unsigned long omap2_dpllcore_recalc(struct clk *clk) { - unsigned long rate; - - rate = omap2xxx_clk_get_core_rate(clk, parent_rate); - - if (rate_storage == CURRENT_RATE) - clk->rate = rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = rate; + return omap2xxx_clk_get_core_rate(clk); } static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) @@ -221,7 +394,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) struct prcm_config tmpset; const struct dpll_data *dd; - cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck, dpll_ck.parent->rate); + cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); mult &= OMAP24XX_CORE_CLK_SRC_MASK; @@ -243,8 +416,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) if (!dd) return -EINVAL; - tmpset.cm_clksel1_pll = cm_read_mod_reg(clk->prcm_mod, - dd->mult_div1_reg); + tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); tmpset.cm_clksel1_pll &= ~(dd->mult_mask | dd->div1_mask); div = ((curr_prcm_set->xtal_speed / 1000000) - 1); @@ -289,18 +461,9 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) * * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. */ -static void omap2_table_mpu_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) +static unsigned long omap2_table_mpu_recalc(struct clk *clk) { - struct prcm_config *prcm; - unsigned long mpurate; - - mpurate = omap2xxx_clk_find_oppset_by_mpurate(parent_rate, &prcm); - - if (rate_storage == CURRENT_RATE) - clk->rate = mpurate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = mpurate; + return curr_prcm_set->mpu_speed; } /* @@ -340,12 +503,25 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate) { u32 cur_rate, done_rate, bypass = 0, tmp; struct prcm_config *prcm; - unsigned long flags, found_speed; + unsigned long found_speed = 0; + unsigned long flags; if (clk != &virt_prcm_set) return -EINVAL; - found_speed = omap2xxx_clk_find_oppset_by_mpurate(rate, &prcm); + for (prcm = rate_table; prcm->mpu_speed; prcm++) { + if (!(prcm->flags & cpu_mask)) + continue; + + if (prcm->xtal_speed != sys_ck.rate) + continue; + + if (prcm->mpu_speed <= rate) { + found_speed = prcm->mpu_speed; + break; + } + } + if (!found_speed) { printk(KERN_INFO "Could not set MPU rate to %luMHz\n", rate / 1000000); @@ -353,7 +529,7 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate) } curr_prcm_set = prcm; - cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck, dpll_ck.parent->rate); + cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); if (prcm->dpll_speed == cur_rate / 2) { omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); @@ -444,13 +620,11 @@ void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) #endif static struct clk_functions omap2_clk_functions = { - .clk_register = omap2_clk_register, .clk_enable = omap2_clk_enable, .clk_disable = omap2_clk_disable, .clk_round_rate = omap2_clk_round_rate, .clk_set_rate = omap2_clk_set_rate, .clk_set_parent = omap2_clk_set_parent, - .clk_get_parent = omap2_clk_get_parent, .clk_disable_unused = omap2_clk_disable_unused, #ifdef CONFIG_CPU_FREQ .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, @@ -479,39 +653,21 @@ static u32 omap2_get_sysclkdiv(void) { u32 div; - div = prm_read_mod_reg(OMAP24XX_GR_MOD, - OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET); + div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); div &= OMAP_SYSCLKDIV_MASK; div >>= OMAP_SYSCLKDIV_SHIFT; return div; } -static void omap2_osc_clk_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) +static unsigned long omap2_osc_clk_recalc(struct clk *clk) { - unsigned long rate; - - /* XXX osc_ck on 2xxx currently is parentless */ - rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv(); - - if (rate_storage == CURRENT_RATE) - clk->rate = rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = rate; + return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); } -static void omap2_sys_clk_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) +static unsigned long omap2_sys_clk_recalc(struct clk *clk) { - unsigned long rate; - - rate = parent_rate / omap2_get_sysclkdiv(); - - if (rate_storage == CURRENT_RATE) - clk->rate = rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = rate; + return clk->parent->rate / omap2_get_sysclkdiv(); } /* @@ -554,8 +710,8 @@ arch_initcall(omap2_clk_arch_init); int __init omap2_clk_init(void) { struct prcm_config *prcm; - struct clk **clkp; - u32 clkrate; + struct omap_clk *c; + u32 clkrate, cpu_mask; if (cpu_is_omap242x()) cpu_mask = RATE_IN_242X; @@ -564,26 +720,28 @@ int __init omap2_clk_init(void) clk_init(&omap2_clk_functions); - omap2_osc_clk_recalc(&osc_ck, 0, CURRENT_RATE); - omap2_sys_clk_recalc(&sys_ck, sys_ck.parent->rate, CURRENT_RATE); + osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); + propagate_rate(&osc_ck); + sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); + propagate_rate(&sys_ck); - for (clkp = onchip_24xx_clks; - clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); - clkp++) { + for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) + clk_init_one(c->lk.clk); - if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { - clk_register(*clkp); - continue; - } + cpu_mask = 0; + if (cpu_is_omap2420()) + cpu_mask |= CK_242X; + if (cpu_is_omap2430()) + cpu_mask |= CK_243X; - if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) { - clk_register(*clkp); - continue; + for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) + if (c->cpu & cpu_mask) { + clkdev_add(&c->lk); + clk_register(c->lk.clk); } - } /* Check the MPU rate set by bootloader */ - clkrate = omap2xxx_clk_get_core_rate(&dpll_ck, dpll_ck.parent->rate); + clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags & cpu_mask)) continue; diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 2b7b473449a..33c3e5b1432 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -24,20 +24,13 @@ #include "cm-regbits-24xx.h" #include "sdrc.h" -static void omap2_table_mpu_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage); +static unsigned long omap2_table_mpu_recalc(struct clk *clk); static int omap2_select_table_rate(struct clk *clk, unsigned long rate); static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); -static void omap2_sys_clk_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage); -static void omap2_osc_clk_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage); -static void omap2_dpllcore_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage); -static int omap2_clk_fixed_enable(struct clk *clk); -static void omap2_clk_fixed_disable(struct clk *clk); -static int omap2_enable_osc_ck(struct clk *clk); -static void omap2_disable_osc_ck(struct clk *clk); +static unsigned long omap2_sys_clk_recalc(struct clk *clk); +static unsigned long omap2_osc_clk_recalc(struct clk *clk); +static unsigned long omap2_sys_clk_recalc(struct clk *clk); +static unsigned long omap2_dpllcore_recalc(struct clk *clk); static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. @@ -626,38 +619,35 @@ static struct prcm_config rate_table[] = { /* Base external input clocks */ static struct clk func_32k_ck = { .name = "func_32k_ck", + .ops = &clkops_null, .rate = 32000, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .flags = RATE_FIXED, + .clkdm_name = "wkup_clkdm", }; /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ .name = "osc_ck", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "prm_clkdm" }, - .enable = &omap2_enable_osc_ck, - .disable = &omap2_disable_osc_ck, + .ops = &clkops_oscck, + .clkdm_name = "wkup_clkdm", .recalc = &omap2_osc_clk_recalc, }; /* Without modem likely 12MHz, with modem likely 13MHz */ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ .name = "sys_ck", /* ~ ref_clk also */ + .ops = &clkops_null, .parent = &osc_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &omap2_sys_clk_recalc, }; static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .name = "alt_ck", + .ops = &clkops_null, .rate = 54000000, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .flags = RATE_FIXED, + .clkdm_name = "wkup_clkdm", }; /* @@ -670,10 +660,12 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ */ static struct dpll_data dpll_dd = { - .mult_div1_reg = CM_CLKSEL1, + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .mult_mask = OMAP24XX_DPLL_MULT_MASK, .div1_mask = OMAP24XX_DPLL_DIV_MASK, - .control_reg = CM_CLKEN, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP24XX_EN_DPLL_MASK, .max_multiplier = 1024, .min_divider = 1, @@ -687,42 +679,34 @@ static struct dpll_data dpll_dd = { */ static struct clk dpll_ck = { .name = "dpll_ck", + .ops = &clkops_null, .parent = &sys_ck, /* Can be func_32k also */ - .prcm_mod = PLL_MOD, .dpll_data = &dpll_dd, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &omap2_dpllcore_recalc, .set_rate = &omap2_reprogram_dpllcore, }; static struct clk apll96_ck = { .name = "apll96_ck", + .ops = &clkops_fixed, .parent = &sys_ck, - .prcm_mod = PLL_MOD, .rate = 96000000, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ENABLE_ON_INIT, - .clkdm = { .name = "prm_clkdm" }, - .enable_reg = CM_CLKEN, + .flags = RATE_FIXED | ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, - .enable = &omap2_clk_fixed_enable, - .disable = &omap2_clk_fixed_disable, }; static struct clk apll54_ck = { .name = "apll54_ck", + .ops = &clkops_fixed, .parent = &sys_ck, - .prcm_mod = PLL_MOD, .rate = 54000000, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ENABLE_ON_INIT, - .clkdm = { .name = "prm_clkdm" }, - .enable_reg = CM_CLKEN, + .flags = RATE_FIXED | ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, - .enable = &omap2_clk_fixed_enable, - .disable = &omap2_clk_fixed_disable, }; /* @@ -749,13 +733,11 @@ static const struct clksel func_54m_clksel[] = { static struct clk func_54m_ck = { .name = "func_54m_ck", + .ops = &clkops_null, .parent = &apll54_ck, /* can also be alt_clk */ - .prcm_mod = PLL_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, + .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_54M_SOURCE, .clksel = func_54m_clksel, .recalc = &omap2_clksel_recalc, @@ -763,10 +745,9 @@ static struct clk func_54m_ck = { static struct clk core_ck = { .name = "core_ck", + .ops = &clkops_null, .parent = &dpll_ck, /* can also be 32k */ - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED, - .clkdm = { .name = "cm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -790,13 +771,11 @@ static const struct clksel func_96m_clksel[] = { /* The parent of this clock is not selectable on 2420. */ static struct clk func_96m_ck = { .name = "func_96m_ck", + .ops = &clkops_null, .parent = &apll96_ck, - .prcm_mod = PLL_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, + .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP2430_96M_SOURCE, .clksel = func_96m_clksel, .recalc = &omap2_clksel_recalc, @@ -824,13 +803,11 @@ static const struct clksel func_48m_clksel[] = { static struct clk func_48m_ck = { .name = "func_48m_ck", + .ops = &clkops_null, .parent = &apll96_ck, /* 96M or Alt */ - .prcm_mod = PLL_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, + .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_48M_SOURCE, .clksel = func_48m_clksel, .recalc = &omap2_clksel_recalc, @@ -840,20 +817,18 @@ static struct clk func_48m_ck = { static struct clk func_12m_ck = { .name = "func_12m_ck", + .ops = &clkops_null, .parent = &func_48m_ck, .fixed_div = 4, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &omap2_fixed_divisor_recalc, }; /* Secure timer, only available in secure mode */ static struct clk wdt1_osc_ck = { - .name = "wdt1_osc_ck", + .name = "ck_wdt1_osc", + .ops = &clkops_null, /* RMK: missing? */ .parent = &osc_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "prm_clkdm" }, .recalc = &followparent_recalc, }; @@ -895,14 +870,13 @@ static const struct clksel common_clkout_src_clksel[] = { static struct clk sys_clkout_src = { .name = "sys_clkout_src", + .ops = &clkops_omap2_dflt, .parent = &func_54m_ck, - .prcm_mod = OMAP24XX_GR_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "prm_clkdm" }, - .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET, + .clkdm_name = "wkup_clkdm", + .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET, + .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, .clksel = common_clkout_src_clksel, .recalc = &omap2_clksel_recalc, @@ -926,12 +900,10 @@ static const struct clksel sys_clkout_clksel[] = { static struct clk sys_clkout = { .name = "sys_clkout", + .ops = &clkops_null, .parent = &sys_clkout_src, - .prcm_mod = OMAP24XX_GR_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "prm_clkdm" }, - .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET, + .clkdm_name = "wkup_clkdm", + .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, .clksel = sys_clkout_clksel, .recalc = &omap2_clksel_recalc, @@ -942,14 +914,13 @@ static struct clk sys_clkout = { /* In 2430, new in 2420 ES2 */ static struct clk sys_clkout2_src = { .name = "sys_clkout2_src", + .ops = &clkops_omap2_dflt, .parent = &func_54m_ck, - .prcm_mod = OMAP24XX_GR_MOD, - .flags = CLOCK_IN_OMAP242X, - .clkdm = { .name = "cm_clkdm" }, - .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET, + .clkdm_name = "wkup_clkdm", + .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET, + .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, .clksel = common_clkout_src_clksel, .recalc = &omap2_clksel_recalc, @@ -965,11 +936,10 @@ static const struct clksel sys_clkout2_clksel[] = { /* In 2430, new in 2420 ES2 */ static struct clk sys_clkout2 = { .name = "sys_clkout2", + .ops = &clkops_null, .parent = &sys_clkout2_src, - .prcm_mod = OMAP24XX_GR_MOD, - .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, - .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET, + .clkdm_name = "wkup_clkdm", + .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, .clksel = sys_clkout2_clksel, .recalc = &omap2_clksel_recalc, @@ -979,11 +949,10 @@ static struct clk sys_clkout2 = { static struct clk emul_ck = { .name = "emul_ck", + .ops = &clkops_omap2_dflt, .parent = &func_54m_ck, - .prcm_mod = OMAP24XX_GR_MOD, - .flags = CLOCK_IN_OMAP242X, - .clkdm = { .name = "cm_clkdm" }, - .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET, + .clkdm_name = "wkup_clkdm", + .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, .recalc = &followparent_recalc, @@ -1015,16 +984,17 @@ static const struct clksel mpu_clksel[] = { static struct clk mpu_ck = { /* Control cpu */ .name = "mpu_ck", + .ops = &clkops_null, .parent = &core_ck, - .prcm_mod = MPU_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | DELAYED_APP, - .clkdm = { .name = "mpu_clkdm" }, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, + .clkdm_name = "mpu_clkdm", .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, .clksel = mpu_clksel, .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate }; /* @@ -1056,16 +1026,18 @@ static const struct clksel dsp_fck_clksel[] = { static struct clk dsp_fck = { .name = "dsp_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, - .prcm_mod = OMAP24XX_DSP_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP, - .clkdm = { .name = "dsp_clkdm" }, - .enable_reg = CM_FCLKEN, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, + .clkdm_name = "dsp_clkdm", + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, .clksel = dsp_fck_clksel, .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate }; /* DSP interface clock */ @@ -1084,36 +1056,34 @@ static const struct clksel dsp_irate_ick_clksel[] = { /* This clock does not exist as such in the TRM. */ static struct clk dsp_irate_ick = { .name = "dsp_irate_ick", + .ops = &clkops_null, .parent = &dsp_fck, - .prcm_mod = OMAP24XX_DSP_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | - PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dsp_clkdm" }, - .clksel_reg = CM_CLKSEL, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, + .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, .clksel = dsp_irate_ick_clksel, .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate }; /* 2420 only */ static struct clk dsp_ick = { .name = "dsp_ick", /* apparently ipi and isp */ + .ops = &clkops_omap2_dflt_wait, .parent = &dsp_irate_ick, - .prcm_mod = OMAP24XX_DSP_MOD, - .flags = CLOCK_IN_OMAP242X | DELAYED_APP, - .clkdm = { .name = "dsp_clkdm" }, - .enable_reg = CM_ICLKEN, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ }; /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ static struct clk iva2_1_ick = { .name = "iva2_1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &dsp_irate_ick, - .prcm_mod = OMAP24XX_DSP_MOD, - .flags = CLOCK_IN_OMAP243X | DELAYED_APP, - .clkdm = { .name = "dsp_clkdm" }, - .enable_reg = CM_FCLKEN, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, }; @@ -1124,13 +1094,13 @@ static struct clk iva2_1_ick = { */ static struct clk iva1_ifck = { .name = "iva1_ifck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, - .prcm_mod = OMAP24XX_DSP_MOD, - .flags = CLOCK_IN_OMAP242X | DELAYED_APP, - .clkdm = { .name = "iva1_clkdm" }, - .enable_reg = CM_FCLKEN, + .flags = CONFIG_PARTICIPANT | DELAYED_APP, + .clkdm_name = "iva1_clkdm", + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, .clksel = dsp_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -1141,11 +1111,10 @@ static struct clk iva1_ifck = { /* IVA1 mpu/int/i/f clocks are /2 of parent */ static struct clk iva1_mpu_int_ifck = { .name = "iva1_mpu_int_ifck", + .ops = &clkops_omap2_dflt_wait, .parent = &iva1_ifck, - .prcm_mod = OMAP24XX_DSP_MOD, - .flags = CLOCK_IN_OMAP242X, - .clkdm = { .name = "iva1_clkdm" }, - .enable_reg = CM_FCLKEN, + .clkdm_name = "iva1_clkdm", + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, .fixed_div = 2, .recalc = &omap2_fixed_divisor_recalc, @@ -1188,15 +1157,16 @@ static const struct clksel core_l3_clksel[] = { static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ .name = "core_l3_ck", + .ops = &clkops_null, .parent = &core_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | DELAYED_APP, - .clkdm = { .name = "core_l3_clkdm" }, - .clksel_reg = CM_CLKSEL1, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, + .clkdm_name = "core_l3_clkdm", + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, .clksel = core_l3_clksel, .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate }; /* usb_l4_ick */ @@ -1215,18 +1185,18 @@ static const struct clksel usb_l4_ick_clksel[] = { /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ static struct clk usb_l4_ick = { /* FS-USB interface clock */ .name = "usb_l4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY | - DELAYED_APP, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN2, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP24XX_EN_USB_SHIFT, - .idlest_bit = OMAP24XX_ST_USB_SHIFT, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, .clksel = usb_l4_ick_clksel, .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate }; /* @@ -1249,12 +1219,11 @@ static const struct clksel l4_clksel[] = { static struct clk l4_ck = { /* used both as an ick and fck */ .name = "l4_ck", + .ops = &clkops_null, .parent = &core_l3_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | DELAYED_APP, - .clkdm = { .name = "core_l4_clkdm" }, - .clksel_reg = CM_CLKSEL1, + .flags = DELAYED_APP, + .clkdm_name = "core_l4_clkdm", + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, .clksel = l4_clksel, .recalc = &omap2_clksel_recalc, @@ -1288,15 +1257,13 @@ static const struct clksel ssi_ssr_sst_fck_clksel[] = { static struct clk ssi_ssr_sst_fck = { .name = "ssi_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY | - DELAYED_APP, - .clkdm = { .name = "core_l3_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .flags = DELAYED_APP, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .idlest_bit = OMAP24XX_ST_SSI_SHIFT, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, .clksel = ssi_ssr_sst_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -1310,13 +1277,11 @@ static struct clk ssi_ssr_sst_fck = { */ static struct clk ssi_l4_ick = { .name = "ssi_l4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .clkdm = { .name = "core_l4_clkdm" }, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .enable_reg = CM_ICLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .idlest_bit = OMAP24XX_ST_SSI_SHIFT, .recalc = &followparent_recalc, }; @@ -1332,7 +1297,7 @@ static struct clk ssi_l4_ick = { * divided value of fclk. * */ -/* XXX REVISIT: GFX clock is part of the table rate set also? doublecheck. */ +/* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */ /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ static const struct clksel gfx_fck_clksel[] = { @@ -1342,13 +1307,12 @@ static const struct clksel gfx_fck_clksel[] = { static struct clk gfx_3d_fck = { .name = "gfx_3d_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, - .prcm_mod = GFX_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "gfx_clkdm" }, - .enable_reg = CM_FCLKEN, + .clkdm_name = "gfx_clkdm", + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_3D_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_mask = OMAP_CLKSEL_GFX_MASK, .clksel = gfx_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -1358,13 +1322,12 @@ static struct clk gfx_3d_fck = { static struct clk gfx_2d_fck = { .name = "gfx_2d_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, - .prcm_mod = GFX_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "gfx_clkdm" }, - .enable_reg = CM_FCLKEN, + .clkdm_name = "gfx_clkdm", + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_2D_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_mask = OMAP_CLKSEL_GFX_MASK, .clksel = gfx_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -1374,11 +1337,10 @@ static struct clk gfx_2d_fck = { static struct clk gfx_ick = { .name = "gfx_ick", /* From l3 */ + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, - .prcm_mod = GFX_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "gfx_clkdm" }, - .enable_reg = CM_ICLKEN, + .clkdm_name = "gfx_clkdm", + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), .enable_bit = OMAP_EN_GFX_SHIFT, .recalc = &followparent_recalc, }; @@ -1405,25 +1367,26 @@ static const struct clksel mdm_ick_clksel[] = { static struct clk mdm_ick = { /* used both as a ick and fck */ .name = "mdm_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, - .prcm_mod = OMAP2430_MDM_MOD, - .flags = CLOCK_IN_OMAP243X | DELAYED_APP, - .clkdm = { .name = "mdm_clkdm" }, - .enable_reg = CM_ICLKEN, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, + .clkdm_name = "mdm_clkdm", + .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, .clksel = mdm_ick_clksel, .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate }; static struct clk mdm_osc_ck = { .name = "mdm_osc_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &osc_ck, - .prcm_mod = OMAP2430_MDM_MOD, - .flags = CLOCK_IN_OMAP243X, - .clkdm = { .name = "mdm_clkdm" }, - .enable_reg = CM_FCLKEN, + .clkdm_name = "mdm_clkdm", + .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), .enable_bit = OMAP2430_EN_OSC_SHIFT, .recalc = &followparent_recalc, }; @@ -1465,26 +1428,24 @@ static const struct clksel dss1_fck_clksel[] = { static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ .name = "dss_ick", + .ops = &clkops_omap2_dflt, .parent = &l4_ck, /* really both l3 and l4 */ - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "dss_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "dss_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_DSS1_SHIFT, .recalc = &followparent_recalc, }; static struct clk dss1_fck = { .name = "dss1_fck", + .ops = &clkops_omap2_dflt, .parent = &core_ck, /* Core or sys */ - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - DELAYED_APP, - .clkdm = { .name = "dss_clkdm" }, - .enable_reg = CM_FCLKEN1, + .flags = DELAYED_APP, + .clkdm_name = "dss_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_DSS1_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, .clksel = dss1_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -1510,15 +1471,14 @@ static const struct clksel dss2_fck_clksel[] = { static struct clk dss2_fck = { /* Alt clk used in power management */ .name = "dss2_fck", + .ops = &clkops_omap2_dflt, .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - DELAYED_APP, - .clkdm = { .name = "dss_clkdm" }, - .enable_reg = CM_FCLKEN1, + .flags = DELAYED_APP, + .clkdm_name = "dss_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_DSS2_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, .clksel = dss2_fck_clksel, .recalc = &followparent_recalc, @@ -1526,11 +1486,10 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ static struct clk dss_54m_fck = { /* Alt clk used in power management */ .name = "dss_54m_fck", /* 54m tv clk */ + .ops = &clkops_omap2_dflt_wait, .parent = &func_54m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "dss_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "dss_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_TV_SHIFT, .recalc = &followparent_recalc, }; @@ -1555,26 +1514,23 @@ static const struct clksel omap24xx_gpt_clksel[] = { static struct clk gpt1_ick = { .name = "gpt1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = WKUP_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_GPT1_SHIFT, - .idlest_bit = OMAP24XX_ST_GPT1_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpt1_fck = { .name = "gpt1_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = WKUP_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_GPT1_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1584,26 +1540,23 @@ static struct clk gpt1_fck = { static struct clk gpt2_ick = { .name = "gpt2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT2_SHIFT, - .idlest_bit = OMAP24XX_ST_GPT2_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpt2_fck = { .name = "gpt2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT2_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL2, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1611,26 +1564,23 @@ static struct clk gpt2_fck = { static struct clk gpt3_ick = { .name = "gpt3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT3_SHIFT, - .idlest_bit = OMAP24XX_ST_GPT3_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpt3_fck = { .name = "gpt3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT3_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL2, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1638,26 +1588,23 @@ static struct clk gpt3_fck = { static struct clk gpt4_ick = { .name = "gpt4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT4_SHIFT, - .idlest_bit = OMAP24XX_ST_GPT4_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpt4_fck = { .name = "gpt4_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT4_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL2, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1665,26 +1612,23 @@ static struct clk gpt4_fck = { static struct clk gpt5_ick = { .name = "gpt5_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT5_SHIFT, - .idlest_bit = OMAP24XX_ST_GPT5_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpt5_fck = { .name = "gpt5_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT5_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL2, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1692,26 +1636,23 @@ static struct clk gpt5_fck = { static struct clk gpt6_ick = { .name = "gpt6_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT6_SHIFT, - .idlest_bit = OMAP24XX_ST_GPT6_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpt6_fck = { .name = "gpt6_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT6_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL2, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1719,26 +1660,22 @@ static struct clk gpt6_fck = { static struct clk gpt7_ick = { .name = "gpt7_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT7_SHIFT, - .idlest_bit = OMAP24XX_ST_GPT7_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpt7_fck = { .name = "gpt7_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT7_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL2, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1746,26 +1683,23 @@ static struct clk gpt7_fck = { static struct clk gpt8_ick = { .name = "gpt8_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT8_SHIFT, - .idlest_bit = OMAP24XX_ST_GPT8_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpt8_fck = { .name = "gpt8_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT8_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL2, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1773,26 +1707,23 @@ static struct clk gpt8_fck = { static struct clk gpt9_ick = { .name = "gpt9_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT9_SHIFT, - .idlest_bit = OMAP24XX_ST_GPT9_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpt9_fck = { .name = "gpt9_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT9_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL2, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1800,26 +1731,23 @@ static struct clk gpt9_fck = { static struct clk gpt10_ick = { .name = "gpt10_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT10_SHIFT, - .idlest_bit = OMAP24XX_ST_GPT10_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpt10_fck = { .name = "gpt10_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT10_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL2, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1827,26 +1755,23 @@ static struct clk gpt10_fck = { static struct clk gpt11_ick = { .name = "gpt11_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT11_SHIFT, - .idlest_bit = OMAP24XX_ST_GPT11_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpt11_fck = { .name = "gpt11_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT11_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL2, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1854,26 +1779,23 @@ static struct clk gpt11_fck = { static struct clk gpt12_ick = { .name = "gpt12_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT12_SHIFT, - .idlest_bit = OMAP24XX_ST_GPT12_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpt12_fck = { .name = "gpt12_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT12_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL2, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1881,381 +1803,328 @@ static struct clk gpt12_fck = { static struct clk mcbsp1_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .idlest_bit = OMAP24XX_ST_MCBSP1_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcbsp1_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcbsp2_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .idlest_bit = OMAP24XX_ST_MCBSP2_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcbsp2_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcbsp3_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, - .idlest_bit = OMAP2430_ST_MCBSP3_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcbsp3_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcbsp4_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 4, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, - .idlest_bit = OMAP2430_ST_MCBSP4_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcbsp4_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 4, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcbsp5_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 5, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, - .idlest_bit = OMAP2430_ST_MCBSP5_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcbsp5_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 5, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcspi1_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .clkdm = { .name = "core_l4_clkdm" }, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .idlest_bit = OMAP24XX_ST_MCSPI1_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcspi1_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_48m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcspi2_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .idlest_bit = OMAP24XX_ST_MCSPI2_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcspi2_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &func_48m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcspi3_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, - .idlest_bit = OMAP2430_ST_MCSPI3_SHIFT, .recalc = &followparent_recalc, }; static struct clk mcspi3_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &func_48m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, .recalc = &followparent_recalc, }; static struct clk uart1_ick = { .name = "uart1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .idlest_bit = OMAP24XX_ST_UART1_SHIFT, .recalc = &followparent_recalc, }; static struct clk uart1_fck = { .name = "uart1_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_48m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_UART1_SHIFT, .recalc = &followparent_recalc, }; static struct clk uart2_ick = { .name = "uart2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .idlest_bit = OMAP24XX_ST_UART2_SHIFT, .recalc = &followparent_recalc, }; static struct clk uart2_fck = { .name = "uart2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_48m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_UART2_SHIFT, .recalc = &followparent_recalc, }; static struct clk uart3_ick = { .name = "uart3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .idlest_bit = OMAP24XX_ST_UART3_SHIFT, .recalc = &followparent_recalc, }; static struct clk uart3_fck = { .name = "uart3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_48m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP24XX_EN_UART3_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpios_ick = { .name = "gpios_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = WKUP_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .idlest_bit = OMAP24XX_ST_GPIOS_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpios_fck = { .name = "gpios_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = WKUP_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, - .enable_reg = CM_FCLKEN, + .clkdm_name = "wkup_clkdm", + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .idlest_bit = OMAP24XX_ST_GPIOS_SHIFT, .recalc = &followparent_recalc, }; -/* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */ static struct clk mpu_wdt_ick = { .name = "mpu_wdt_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = WKUP_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, - .enable_reg = CM_ICLKEN, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .idlest_bit = OMAP24XX_ST_MPU_WDT_SHIFT, .recalc = &followparent_recalc, }; -/* aka WDT2 */ static struct clk mpu_wdt_fck = { .name = "mpu_wdt_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = WKUP_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, - .enable_reg = CM_FCLKEN, + .clkdm_name = "wkup_clkdm", + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .idlest_bit = OMAP24XX_ST_MPU_WDT_SHIFT, .recalc = &followparent_recalc, }; static struct clk sync_32k_ick = { .name = "sync_32k_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = WKUP_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ENABLE_ON_INIT | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, - .idlest_bit = OMAP24XX_ST_32KSYNC_SHIFT, .recalc = &followparent_recalc, }; -/* REVISIT: parent is really wu_l4_iclk */ static struct clk wdt1_ick = { .name = "wdt1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = WKUP_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "prm_clkdm" }, - .enable_reg = CM_ICLKEN, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_WDT1_SHIFT, - .idlest_bit = OMAP24XX_ST_WDT1_SHIFT, .recalc = &followparent_recalc, }; static struct clk omapctrl_ick = { .name = "omapctrl_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = WKUP_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ENABLE_ON_INIT, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, - .idlest_bit = OMAP24XX_ST_OMAPCTRL_SHIFT, .recalc = &followparent_recalc, }; static struct clk icr_ick = { .name = "icr_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = WKUP_MOD, - .flags = CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP2430_EN_ICR_SHIFT, - .idlest_bit = OMAP2430_ST_ICR_SHIFT, .recalc = &followparent_recalc, }; static struct clk cam_ick = { .name = "cam_ick", + .ops = &clkops_omap2_dflt, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_CAM_SHIFT, .recalc = &followparent_recalc, }; @@ -2267,304 +2136,262 @@ static struct clk cam_ick = { */ static struct clk cam_fck = { .name = "cam_fck", + .ops = &clkops_omap2_dflt, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l3_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_CAM_SHIFT, .recalc = &followparent_recalc, }; static struct clk mailboxes_ick = { .name = "mailboxes_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, - .idlest_bit = OMAP24XX_ST_MAILBOXES_SHIFT, .recalc = &followparent_recalc, }; static struct clk wdt4_ick = { .name = "wdt4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .idlest_bit = OMAP24XX_ST_WDT4_SHIFT, .recalc = &followparent_recalc, }; static struct clk wdt4_fck = { .name = "wdt4_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_WDT4_SHIFT, .recalc = &followparent_recalc, }; static struct clk wdt3_ick = { .name = "wdt3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_WDT3_SHIFT, - .idlest_bit = OMAP2420_ST_WDT3_SHIFT, .recalc = &followparent_recalc, }; static struct clk wdt3_fck = { .name = "wdt3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_WDT3_SHIFT, - .enable_bit = OMAP2420_ST_WDT3_SHIFT, .recalc = &followparent_recalc, }; static struct clk mspro_ick = { .name = "mspro_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .idlest_bit = OMAP24XX_ST_MSPRO_SHIFT, .recalc = &followparent_recalc, }; static struct clk mspro_fck = { .name = "mspro_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .idlest_bit = OMAP24XX_ST_MSPRO_SHIFT, .recalc = &followparent_recalc, }; static struct clk mmc_ick = { .name = "mmc_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_MMC_SHIFT, - .idlest_bit = OMAP2420_ST_MMC_SHIFT, .recalc = &followparent_recalc, }; static struct clk mmc_fck = { .name = "mmc_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_MMC_SHIFT, - .idlest_bit = OMAP2420_ST_MMC_SHIFT, .recalc = &followparent_recalc, }; static struct clk fac_ick = { .name = "fac_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .idlest_bit = OMAP24XX_ST_FAC_SHIFT, .recalc = &followparent_recalc, }; static struct clk fac_fck = { .name = "fac_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_12m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .idlest_bit = OMAP24XX_ST_FAC_SHIFT, .recalc = &followparent_recalc, }; static struct clk eac_ick = { .name = "eac_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_EAC_SHIFT, - .idlest_bit = OMAP2420_ST_EAC_SHIFT, .recalc = &followparent_recalc, }; static struct clk eac_fck = { .name = "eac_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_EAC_SHIFT, - .idlest_bit = OMAP2420_ST_EAC_SHIFT, .recalc = &followparent_recalc, }; static struct clk hdq_ick = { .name = "hdq_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .idlest_bit = OMAP24XX_ST_HDQ_SHIFT, .recalc = &followparent_recalc, }; static struct clk hdq_fck = { .name = "hdq_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_12m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .idlest_bit = OMAP24XX_ST_HDQ_SHIFT, .recalc = &followparent_recalc, }; static struct clk i2c2_ick = { .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .idlest_bit = OMAP2420_ST_I2C2_SHIFT, .recalc = &followparent_recalc, }; static struct clk i2c2_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &func_12m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .idlest_bit = OMAP2420_ST_I2C2_SHIFT, .recalc = &followparent_recalc, }; static struct clk i2chs2_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, .recalc = &followparent_recalc, }; static struct clk i2c1_ick = { .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .idlest_bit = OMAP2420_ST_I2C1_SHIFT, .recalc = &followparent_recalc, }; static struct clk i2c1_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_12m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_FCLKEN1, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .idlest_bit = OMAP2420_ST_I2C1_SHIFT, .recalc = &followparent_recalc, }; static struct clk i2chs1_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpmc_fck = { .name = "gpmc_fck", + .ops = &clkops_null, /* RMK: missing? */ .parent = &core_l3_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ENABLE_ON_INIT, - .clkdm = { .name = "core_l3_clkdm" }, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; static struct clk sdma_fck = { .name = "sdma_fck", + .ops = &clkops_null, /* RMK: missing? */ .parent = &core_l3_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l3_clkdm" }, + .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; static struct clk sdma_ick = { .name = "sdma_ick", + .ops = &clkops_null, /* RMK: missing? */ .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l3_clkdm" }, + .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; static struct clk vlynq_ick = { .name = "vlynq_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l3_clkdm" }, - .enable_reg = CM_ICLKEN1, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, - .idlest_bit = OMAP2420_ST_VLYNQ_SHIFT, .recalc = &followparent_recalc, }; @@ -2595,15 +2422,14 @@ static const struct clksel vlynq_fck_clksel[] = { static struct clk vlynq_fck = { .name = "vlynq_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP242X | DELAYED_APP | WAIT_READY, - .clkdm = { .name = "core_l3_clkdm" }, - .enable_reg = CM_FCLKEN1, + .flags = DELAYED_APP, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, - .idlest_bit = OMAP2420_ST_VLYNQ_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, .clksel = vlynq_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -2613,202 +2439,173 @@ static struct clk vlynq_fck = { static struct clk sdrc_ick = { .name = "sdrc_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | WAIT_READY | ENABLE_ON_INIT, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN3, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP2430_EN_SDRC_SHIFT, - .idlest_bit = OMAP2430_ST_SDRC_SHIFT, .recalc = &followparent_recalc, }; static struct clk des_ick = { .name = "des_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_ICLKEN4, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_DES_SHIFT, - .idlest_bit = OMAP24XX_ST_DES_SHIFT, .recalc = &followparent_recalc, }; static struct clk sha_ick = { .name = "sha_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_ICLKEN4, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_SHA_SHIFT, - .idlest_bit = OMAP24XX_ST_SHA_SHIFT, .recalc = &followparent_recalc, }; static struct clk rng_ick = { .name = "rng_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_ICLKEN4, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_RNG_SHIFT, - .idlest_bit = OMAP24XX_ST_RNG_SHIFT, .recalc = &followparent_recalc, }; static struct clk aes_ick = { .name = "aes_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_ICLKEN4, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_AES_SHIFT, - .idlest_bit = OMAP24XX_ST_AES_SHIFT, .recalc = &followparent_recalc, }; static struct clk pka_ick = { .name = "pka_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_ICLKEN4, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_PKA_SHIFT, - .idlest_bit = OMAP24XX_ST_PKA_SHIFT, .recalc = &followparent_recalc, }; static struct clk usb_fck = { .name = "usb_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_48m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY, - .clkdm = { .name = "core_l3_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP24XX_EN_USB_SHIFT, - .idlest_bit = OMAP24XX_ST_USB_SHIFT, .recalc = &followparent_recalc, }; static struct clk usbhs_ick = { .name = "usbhs_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l3_clkdm" }, - .enable_reg = CM_ICLKEN2, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_USBHS_SHIFT, - .idlest_bit = OMAP2430_ST_USBHS_SHIFT, .recalc = &followparent_recalc, }; static struct clk mmchs1_ick = { .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, - .idlest_bit = OMAP2430_ST_MMCHS1_SHIFT, .recalc = &followparent_recalc, }; static struct clk mmchs1_fck = { .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l3_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, .recalc = &followparent_recalc, }; static struct clk mmchs2_ick = { .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, - .idlest_bit = OMAP2430_ST_MMCHS2_SHIFT, .recalc = &followparent_recalc, }; static struct clk mmchs2_fck = { .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_96m_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpio5_ick = { .name = "gpio5_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_GPIO5_SHIFT, - .idlest_bit = OMAP2430_ST_GPIO5_SHIFT, .recalc = &followparent_recalc, }; static struct clk gpio5_fck = { .name = "gpio5_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_GPIO5_SHIFT, .recalc = &followparent_recalc, }; static struct clk mdm_intc_ick = { .name = "mdm_intc_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = CM_ICLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, - .idlest_bit = OMAP2430_ST_MDM_INTC_SHIFT, .recalc = &followparent_recalc, }; static struct clk mmchsdb1_fck = { .name = "mmchsdb_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, .recalc = &followparent_recalc, }; static struct clk mmchsdb2_fck = { .name = "mmchsdb_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_32k_ck, - .prcm_mod = CORE_MOD, - .flags = CLOCK_IN_OMAP243X, - .clkdm = { .name = "core_l4_clkdm" }, - .enable_reg = OMAP24XX_CM_FCLKEN2, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, .recalc = &followparent_recalc, }; @@ -2829,168 +2626,13 @@ static struct clk mmchsdb2_fck = { */ static struct clk virt_prcm_set = { .name = "virt_prcm_set", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | DELAYED_APP, - .clkdm = { .name = "virt_opp_clkdm" }, + .ops = &clkops_null, + .flags = DELAYED_APP, .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ .set_rate = &omap2_select_table_rate, .round_rate = &omap2_round_to_table_rate, }; -static struct clk *onchip_24xx_clks[] __initdata = { - /* external root sources */ - &func_32k_ck, - &osc_ck, - &sys_ck, - &alt_ck, - /* internal analog sources */ - &dpll_ck, - &apll96_ck, - &apll54_ck, - /* internal prcm root sources */ - &func_54m_ck, - &core_ck, - &func_96m_ck, - &func_48m_ck, - &func_12m_ck, - &wdt1_osc_ck, - &sys_clkout_src, - &sys_clkout, - &sys_clkout2_src, - &sys_clkout2, - &emul_ck, - /* mpu domain clocks */ - &mpu_ck, - /* dsp domain clocks */ - &dsp_fck, - &dsp_irate_ick, - &dsp_ick, /* 242x */ - &iva2_1_ick, /* 243x */ - &iva1_ifck, /* 242x */ - &iva1_mpu_int_ifck, /* 242x */ - /* GFX domain clocks */ - &gfx_3d_fck, - &gfx_2d_fck, - &gfx_ick, - /* Modem domain clocks */ - &mdm_ick, - &mdm_osc_ck, - /* DSS domain clocks */ - &dss_ick, - &dss1_fck, - &dss2_fck, - &dss_54m_fck, - /* L3 domain clocks */ - &core_l3_ck, - &ssi_ssr_sst_fck, - &usb_l4_ick, - /* L4 domain clocks */ - &l4_ck, /* used as both core_l4 and wu_l4 */ - &ssi_l4_ick, - /* virtual meta-group clock */ - &virt_prcm_set, - /* general l4 interface ck, multi-parent functional clk */ - &gpt1_ick, - &gpt1_fck, - &gpt2_ick, - &gpt2_fck, - &gpt3_ick, - &gpt3_fck, - &gpt4_ick, - &gpt4_fck, - &gpt5_ick, - &gpt5_fck, - &gpt6_ick, - &gpt6_fck, - &gpt7_ick, - &gpt7_fck, - &gpt8_ick, - &gpt8_fck, - &gpt9_ick, - &gpt9_fck, - &gpt10_ick, - &gpt10_fck, - &gpt11_ick, - &gpt11_fck, - &gpt12_ick, - &gpt12_fck, - &mcbsp1_ick, - &mcbsp1_fck, - &mcbsp2_ick, - &mcbsp2_fck, - &mcbsp3_ick, - &mcbsp3_fck, - &mcbsp4_ick, - &mcbsp4_fck, - &mcbsp5_ick, - &mcbsp5_fck, - &mcspi1_ick, - &mcspi1_fck, - &mcspi2_ick, - &mcspi2_fck, - &mcspi3_ick, - &mcspi3_fck, - &uart1_ick, - &uart1_fck, - &uart2_ick, - &uart2_fck, - &uart3_ick, - &uart3_fck, - &gpios_ick, - &gpios_fck, - &mpu_wdt_ick, - &mpu_wdt_fck, - &sync_32k_ick, - &wdt1_ick, - &omapctrl_ick, - &icr_ick, - &cam_fck, - &cam_ick, - &mailboxes_ick, - &wdt4_ick, - &wdt4_fck, - &wdt3_ick, - &wdt3_fck, - &mspro_ick, - &mspro_fck, - &mmc_ick, - &mmc_fck, - &fac_ick, - &fac_fck, - &eac_ick, - &eac_fck, - &hdq_ick, - &hdq_fck, - &i2c1_ick, - &i2c1_fck, - &i2chs1_fck, - &i2c2_ick, - &i2c2_fck, - &i2chs2_fck, - &gpmc_fck, - &sdma_fck, - &sdma_ick, - &vlynq_ick, - &vlynq_fck, - &sdrc_ick, - &des_ick, - &sha_ick, - &rng_ick, - &aes_ick, - &pka_ick, - &usb_fck, - &usbhs_ick, - &mmchs1_ick, - &mmchs1_fck, - &mmchs2_ick, - &mmchs2_fck, - &gpio5_ick, - &gpio5_fck, - &mdm_intc_ick, - &mmchsdb1_fck, - &mmchsdb2_fck, -}; - #endif diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index f7ac5c1c7c0..0a14dca31e3 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -30,15 +30,251 @@ #include #include #include +#include #include #include "clock.h" -#include "clock34xx.h" #include "prm.h" #include "prm-regbits-34xx.h" #include "cm.h" #include "cm-regbits-34xx.h" +static const struct clkops clkops_noncore_dpll_ops; + +#include "clock34xx.h" + +struct omap_clk { + u32 cpu; + struct clk_lookup lk; +}; + +#define CLK(dev, con, ck, cp) \ + { \ + .cpu = cp, \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + }, \ + } + +#define CK_343X (1 << 0) +#define CK_3430ES1 (1 << 1) +#define CK_3430ES2 (1 << 2) + +static struct omap_clk omap34xx_clks[] = { + CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X), + CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X), + CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X), + CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2), + CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X), + CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X), + CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X), + CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X), + CLK(NULL, "sys_ck", &sys_ck, CK_343X), + CLK(NULL, "sys_altclk", &sys_altclk, CK_343X), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X), + CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X), + CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X), + CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X), + CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X), + CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), + CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), + CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X), + CLK(NULL, "core_ck", &core_ck, CK_343X), + CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X), + CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X), + CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X), + CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X), + CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X), + CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X), + CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X), + CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X), + CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), + CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), + CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), + CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), + CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), + CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), + CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X), + CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X), + CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X), + CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X), + CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X), + CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X), + CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X), + CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X), + CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X), + CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X), + CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), + CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), + CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), + CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), + CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), + CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), + CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X), + CLK(NULL, "mpu_ck", &mpu_ck, CK_343X), + CLK(NULL, "arm_fck", &arm_fck, CK_343X), + CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X), + CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), + CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), + CLK(NULL, "l3_ick", &l3_ick, CK_343X), + CLK(NULL, "l4_ick", &l4_ick, CK_343X), + CLK(NULL, "rm_ick", &rm_ick, CK_343X), + CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), + CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), + CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), + CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), + CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), + CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), + CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), + CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), + CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), + CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2), + CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2), + CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X), + CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2), + CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X), + CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), + CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X), + CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X), + CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X), + CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X), + CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X), + CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X), + CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X), + CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X), + CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X), + CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X), + CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_343X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_343X), + CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), + CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), + CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), + CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X), + CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X), + CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), + CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), + CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), + CLK(NULL, "pka_ick", &pka_ick, CK_343X), + CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X), + CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2), + CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2), + CLK(NULL, "icr_ick", &icr_ick, CK_343X), + CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), + CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), + CLK(NULL, "des2_ick", &des2_ick, CK_343X), + CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X), + CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X), + CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X), + CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X), + CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X), + CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X), + CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X), + CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X), + CLK(NULL, "uart2_ick", &uart2_ick, CK_343X), + CLK(NULL, "uart1_ick", &uart1_ick, CK_343X), + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X), + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X), + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X), + CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), + CLK(NULL, "ssi_ick", &ssi_ick, CK_343X), + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), + CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), + CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), + CLK("omap_rng", "ick", &rng_ick, CK_343X), + CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), + CLK(NULL, "des1_ick", &des1_ick, CK_343X), + CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X), + CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X), + CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X), + CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X), + CLK(NULL, "dss_ick", &dss_ick, CK_343X), + CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), + CLK(NULL, "cam_ick", &cam_ick, CK_343X), + CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), + CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2), + CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2), + CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2), + CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X), + CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X), + CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X), + CLK("omap_wdt", "fck", &wdt2_fck, CK_343X), + CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), + CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), + CLK("omap_wdt", "ick", &wdt2_ick, CK_343X), + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X), + CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X), + CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X), + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X), + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X), + CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X), + CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_343X), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X), + CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X), + CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X), + CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X), + CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X), + CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X), + CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X), + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X), + CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X), + CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X), + CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X), + CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X), + CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X), + CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X), + CLK(NULL, "uart3_ick", &uart3_ick, CK_343X), + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X), + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X), + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X), + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X), + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X), + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X), + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X), + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X), + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X), + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X), + CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X), + CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X), + CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X), + CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X), + CLK(NULL, "pclk_fck", &pclk_fck, CK_343X), + CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X), + CLK(NULL, "atclk_fck", &atclk_fck, CK_343X), + CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X), + CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X), + CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), + CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), + CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), + CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X), + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X), + CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X), +}; + /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ #define DPLL_AUTOIDLE_DISABLE 0x0 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 @@ -48,22 +284,12 @@ /** * omap3_dpll_recalc - recalculate DPLL rate * @clk: DPLL struct clk - * @parent_rate: rate of the DPLL's parent clock - * @rate_storage: flag indicating whether current or temporary rate is changing * * Recalculate and propagate the DPLL rate. */ -static void omap3_dpll_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) +static unsigned long omap3_dpll_recalc(struct clk *clk) { - unsigned long rate; - - rate = omap2_get_dpll_rate(clk, parent_rate); - - if (rate_storage == CURRENT_RATE) - clk->rate = rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = rate; + return omap2_get_dpll_rate(clk); } /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ @@ -74,10 +300,10 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) dd = clk->dpll_data; - v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg); + v = __raw_readl(dd->control_reg); v &= ~dd->enable_mask; v |= clken_bits << __ffs(dd->enable_mask); - cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg); + __raw_writel(v, dd->control_reg); } /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ @@ -91,8 +317,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) state <<= __ffs(dd->idlest_mask); - while (((cm_read_mod_reg(clk->prcm_mod, dd->idlest_reg) - & dd->idlest_mask) != state) && + while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && i < MAX_DPLL_WAIT_TRIES) { i++; udelay(1); @@ -117,7 +342,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) unsigned long fint; u16 f = 0; - fint = clk->parent->rate / (n + 1); + fint = clk->dpll_data->clk_ref->rate / (n + 1); pr_debug("clock: fint is %lu\n", fint); @@ -283,10 +508,16 @@ static int omap3_noncore_dpll_enable(struct clk *clk) if (!dd) return -EINVAL; - if (clk->rate == dd->bypass_clk->rate) + if (clk->rate == dd->clk_bypass->rate) { + WARN_ON(clk->parent != dd->clk_bypass); r = _omap3_noncore_dpll_bypass(clk); - else + } else { + WARN_ON(clk->parent != dd->clk_ref); r = _omap3_noncore_dpll_lock(clk); + } + /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */ + if (!r) + clk->rate = omap2_get_dpll_rate(clk); return r; } @@ -328,43 +559,24 @@ static void omap3_noncore_dpll_disable(struct clk *clk) */ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) { - struct dpll_data *dd; + struct dpll_data *dd = clk->dpll_data; u32 v; - if (!clk) - return -EINVAL; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - /* - * According to the 12-5 CDP code from TI, "Limitation 2.5" - * on 3430ES1 prevents us from changing DPLL multipliers or dividers - * on DPLL4. - */ - if (omap_rev() == OMAP3430_REV_ES1_0 && - !strcmp("dpll4_ck", clk->name)) { - printk(KERN_ERR "clock: DPLL4 cannot change rate due to " - "silicon 'Limitation 2.5' on 3430ES1.\n"); - return -EINVAL; - } - /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ _omap3_noncore_dpll_bypass(clk); /* Set jitter correction */ - v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg); + v = __raw_readl(dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); - cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg); + __raw_writel(v, dd->control_reg); /* Set DPLL multiplier, divider */ - v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg); + v = __raw_readl(dd->mult_div1_reg); v &= ~(dd->mult_mask | dd->div1_mask); v |= m << __ffs(dd->mult_mask); v |= (n - 1) << __ffs(dd->div1_mask); - cm_write_mod_reg(v, clk->prcm_mod, dd->mult_div1_reg); + __raw_writel(v, dd->mult_div1_reg); /* We let the clock framework set the other output dividers later */ @@ -388,6 +600,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) */ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) { + struct clk *new_parent = NULL; u16 freqsel; struct dpll_data *dd; int ret; @@ -399,20 +612,25 @@ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) if (!dd) return -EINVAL; - if (rate == omap2_get_dpll_rate(clk, clk->parent->rate)) + if (rate == omap2_get_dpll_rate(clk)) return 0; - if (dd->bypass_clk->rate == rate && - (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { + /* + * Ensure both the bypass and ref clocks are enabled prior to + * doing anything; we need the bypass clock running to reprogram + * the DPLL. + */ + omap2_clk_enable(dd->clk_bypass); + omap2_clk_enable(dd->clk_ref); + if (dd->clk_bypass->rate == rate && + (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); ret = _omap3_noncore_dpll_bypass(clk); if (!ret) - clk->rate = rate; - + new_parent = dd->clk_bypass; } else { - if (dd->last_rounded_rate != rate) omap2_dpll_round_rate(clk, rate); @@ -428,15 +646,44 @@ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n, freqsel); - if (!ret) - clk->rate = rate; - + new_parent = dd->clk_ref; + } + if (!ret) { + /* + * Switch the parent clock in the heirarchy, and make sure + * that the new parent's usecount is correct. Note: we + * enable the new parent before disabling the old to avoid + * any unnecessary hardware disable->enable transitions. + */ + if (clk->usecount) { + omap2_clk_enable(new_parent); + omap2_clk_disable(clk->parent); + } + clk_reparent(clk, new_parent); + clk->rate = rate; } + omap2_clk_disable(dd->clk_ref); + omap2_clk_disable(dd->clk_bypass); return 0; } +static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) +{ + /* + * According to the 12-5 CDP code from TI, "Limitation 2.5" + * on 3430ES1 prevents us from changing DPLL multipliers or dividers + * on DPLL4. + */ + if (omap_rev() == OMAP3430_REV_ES1_0) { + printk(KERN_ERR "clock: DPLL4 cannot change rate due to " + "silicon 'Limitation 2.5' on 3430ES1.\n"); + return -EINVAL; + } + return omap3_noncore_dpll_set_rate(clk, rate); +} + /* * CORE DPLL (DPLL3) rate programming functions @@ -498,6 +745,11 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) } +static const struct clkops clkops_noncore_dpll_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, +}; + /* DPLL autoidle read/set code */ @@ -519,7 +771,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk) dd = clk->dpll_data; - v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg); + v = __raw_readl(dd->autoidle_reg); v &= dd->autoidle_mask; v >>= __ffs(dd->autoidle_mask); @@ -550,10 +802,10 @@ static void omap3_dpll_allow_idle(struct clk *clk) * by writing 0x5 instead of 0x1. Add some mechanism to * optionally enter this mode. */ - v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg); + v = __raw_readl(dd->autoidle_reg); v &= ~dd->autoidle_mask; v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); - cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg); + __raw_writel(v, dd->autoidle_reg); } /** @@ -572,10 +824,10 @@ static void omap3_dpll_deny_idle(struct clk *clk) dd = clk->dpll_data; - v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg); + v = __raw_readl(dd->autoidle_reg); v &= ~dd->autoidle_mask; v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); - cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg); + __raw_writel(v, dd->autoidle_reg); } /* Clock control for DPLL outputs */ @@ -583,18 +835,15 @@ static void omap3_dpll_deny_idle(struct clk *clk) /** * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate * @clk: DPLL output struct clk - * @parent_rate: rate of the parent clock of @clk - * @rate_storage: flag indicating whether current or temporary rate is changing * * Using parent clock DPLL data, look up DPLL state. If locked, set our * rate to the dpll_clk * 2; otherwise, just use dpll_clk. */ -static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) +static unsigned long omap3_clkoutx2_recalc(struct clk *clk) { const struct dpll_data *dd; - u32 v; unsigned long rate; + u32 v; struct clk *pclk; /* Walk up the parents of clk, looking for a DPLL */ @@ -609,17 +858,13 @@ static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate, WARN_ON(!dd->enable_mask); - rate = parent_rate; - - v = cm_read_mod_reg(pclk->prcm_mod, dd->control_reg) & dd->enable_mask; + v = __raw_readl(dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); - if (v == OMAP3XXX_EN_DPLL_LOCKED) - rate *= 2; - - if (rate_storage == CURRENT_RATE) - clk->rate = rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = rate; + if (v != OMAP3XXX_EN_DPLL_LOCKED) + rate = clk->parent->rate; + else + rate = clk->parent->rate * 2; + return rate; } /* Common clock code */ @@ -631,13 +876,11 @@ static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate, #if defined(CONFIG_ARCH_OMAP3) static struct clk_functions omap2_clk_functions = { - .clk_register = omap2_clk_register, .clk_enable = omap2_clk_enable, .clk_disable = omap2_clk_disable, .clk_round_rate = omap2_clk_round_rate, .clk_set_rate = omap2_clk_set_rate, .clk_set_parent = omap2_clk_set_parent, - .clk_get_parent = omap2_clk_get_parent, .clk_disable_unused = omap2_clk_disable_unused, }; @@ -689,26 +932,13 @@ arch_initcall(omap2_clk_arch_init); int __init omap2_clk_init(void) { /* struct prcm_config *prcm; */ - struct clk **clkp; + struct omap_clk *c; /* u32 clkrate; */ u32 cpu_clkflg; - /* REVISIT: Ultimately this will be used for multiboot */ -#if 0 - if (cpu_is_omap242x()) { - cpu_mask = RATE_IN_242X; - cpu_clkflg = CLOCK_IN_OMAP242X; - clkp = onchip_24xx_clks; - } else if (cpu_is_omap2430()) { - cpu_mask = RATE_IN_243X; - cpu_clkflg = CLOCK_IN_OMAP243X; - clkp = onchip_24xx_clks; - } -#endif if (cpu_is_omap34xx()) { cpu_mask = RATE_IN_343X; - cpu_clkflg = CLOCK_IN_OMAP343X; - clkp = onchip_34xx_clks; + cpu_clkflg = CK_343X; /* * Update this if there are further clock changes between ES2 @@ -716,21 +946,24 @@ int __init omap2_clk_init(void) */ if (omap_rev() == OMAP3430_REV_ES1_0) { /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ - cpu_clkflg |= CLOCK_IN_OMAP3430ES1; + cpu_clkflg |= CK_3430ES1; } else { cpu_mask |= RATE_IN_3430ES2; - cpu_clkflg |= CLOCK_IN_OMAP3430ES2; + cpu_clkflg |= CK_3430ES2; } } clk_init(&omap2_clk_functions); - for (clkp = onchip_34xx_clks; - clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); - clkp++) { - if ((*clkp)->flags & cpu_clkflg) - clk_register(*clkp); - } + for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) + clk_init_one(c->lk.clk); + + for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) + if (c->cpu & cpu_clkflg) { + clkdev_add(&c->lk); + clk_register(c->lk.clk); + omap2_init_clk_clkdm(c->lk.clk); + } /* REVISIT: Not yet ready for OMAP3 */ #if 0 diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 4f462ea8513..70ec10deb65 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -27,16 +27,13 @@ #include "prm.h" #include "prm-regbits-34xx.h" -static void omap3_dpll_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage); -static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage); +static unsigned long omap3_dpll_recalc(struct clk *clk); +static unsigned long omap3_clkoutx2_recalc(struct clk *clk); static void omap3_dpll_allow_idle(struct clk *clk); static void omap3_dpll_deny_idle(struct clk *clk); static u32 omap3_dpll_autoidle_read(struct clk *clk); -static int omap3_noncore_dpll_enable(struct clk *clk); -static void omap3_noncore_dpll_disable(struct clk *clk); static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); +static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); /* Maximum DPLL multiplier, divider values for OMAP3 */ @@ -65,59 +62,59 @@ static struct clk dpll2_fck; /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ static struct clk omap_32k_fck = { .name = "omap_32k_fck", + .ops = &clkops_null, .rate = 32768, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .flags = RATE_FIXED, }; static struct clk secure_32k_fck = { .name = "secure_32k_fck", + .ops = &clkops_null, .rate = 32768, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .flags = RATE_FIXED, }; /* Virtual source clocks for osc_sys_ck */ static struct clk virt_12m_ck = { .name = "virt_12m_ck", + .ops = &clkops_null, .rate = 12000000, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .flags = RATE_FIXED, }; static struct clk virt_13m_ck = { .name = "virt_13m_ck", + .ops = &clkops_null, .rate = 13000000, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .flags = RATE_FIXED, }; static struct clk virt_16_8m_ck = { .name = "virt_16_8m_ck", + .ops = &clkops_null, .rate = 16800000, - .flags = CLOCK_IN_OMAP3430ES2 | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .flags = RATE_FIXED, }; static struct clk virt_19_2m_ck = { .name = "virt_19_2m_ck", + .ops = &clkops_null, .rate = 19200000, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .flags = RATE_FIXED, }; static struct clk virt_26m_ck = { .name = "virt_26m_ck", + .ops = &clkops_null, .rate = 26000000, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .flags = RATE_FIXED, }; static struct clk virt_38_4m_ck = { .name = "virt_38_4m_ck", + .ops = &clkops_null, .rate = 38400000, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .flags = RATE_FIXED, }; static const struct clksel_rate osc_sys_12m_rates[] = { @@ -164,14 +161,13 @@ static const struct clksel osc_sys_clksel[] = { /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ static struct clk osc_sys_ck = { .name = "osc_sys_ck", - .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM, + .ops = &clkops_null, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3_PRM_CLKSEL_OFFSET, + .clksel_reg = OMAP3430_PRM_CLKSEL, .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, .clksel = osc_sys_clksel, /* REVISIT: deal with autoextclkmode? */ - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .flags = RATE_FIXED, .recalc = &omap2_clksel_recalc, }; @@ -190,44 +186,34 @@ static const struct clksel sys_clksel[] = { /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ static struct clk sys_ck = { .name = "sys_ck", + .ops = &clkops_null, .parent = &osc_sys_ck, - .prcm_mod = OMAP3430_GR_MOD | CLK_REG_IN_PRM, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3_PRM_CLKSRC_CTRL_OFFSET, + .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, .clksel_mask = OMAP_SYSCLKDIV_MASK, .clksel = sys_clksel, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, .recalc = &omap2_clksel_recalc, }; static struct clk sys_altclk = { .name = "sys_altclk", - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "cm_clkdm" }, + .ops = &clkops_null, }; -/* - * Optional external clock input for some McBSPs - * Apparently this is not really in prm_clkdm, but rather is fed into - * both CORE and PER separately. - */ +/* Optional external clock input for some McBSPs */ static struct clk mcbsp_clks = { .name = "mcbsp_clks", - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .ops = &clkops_null, }; /* PRM EXTERNAL CLOCK OUTPUT */ static struct clk sys_clkout1 = { .name = "sys_clkout1", + .ops = &clkops_omap2_dflt, .parent = &osc_sys_ck, - .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM, - .enable_reg = OMAP3_PRM_CLKOUT_CTRL_OFFSET, + .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "prm_clkdm" }, .recalc = &followparent_recalc, }; @@ -259,21 +245,22 @@ static const struct clksel_rate div16_dpll_rates[] = { /* MPU clock source */ /* Type: DPLL */ static struct dpll_data dpll1_dd = { - .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL, + .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, + .clk_bypass = &dpll1_fck, + .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, - .control_reg = OMAP3430_CM_CLKEN_PLL, + .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, - .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL, + .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, - .idlest_reg = OMAP3430_CM_IDLEST_PLL, + .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, - .bypass_clk = &dpll1_fck, .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, @@ -282,13 +269,12 @@ static struct dpll_data dpll1_dd = { static struct clk dpll1_ck = { .name = "dpll1_ck", + .ops = &clkops_null, .parent = &sys_ck, - .prcm_mod = MPU_MOD, .dpll_data = &dpll1_dd, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | RECALC_ON_ENABLE, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm = { .name = "dpll1_clkdm" }, + .clkdm_name = "dpll1_clkdm", .recalc = &omap3_dpll_recalc, }; @@ -298,9 +284,9 @@ static struct clk dpll1_ck = { */ static struct clk dpll1_x2_ck = { .name = "dpll1_x2_ck", + .ops = &clkops_null, .parent = &dpll1_ck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll1_clkdm" }, + .clkdm_name = "dpll1_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -316,14 +302,13 @@ static const struct clksel div16_dpll1_x2m2_clksel[] = { */ static struct clk dpll1_x2m2_ck = { .name = "dpll1_x2m2_ck", + .ops = &clkops_null, .parent = &dpll1_x2_ck, - .prcm_mod = MPU_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_CM_CLKSEL2_PLL, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll1_x2m2_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll1_clkdm" }, + .clkdm_name = "dpll1_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -332,22 +317,23 @@ static struct clk dpll1_x2m2_ck = { /* Type: DPLL */ static struct dpll_data dpll2_dd = { - .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL, + .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, + .clk_bypass = &dpll2_fck, + .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, - .control_reg = OMAP3430_CM_CLKEN_PLL, + .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | (1 << DPLL_LOW_POWER_BYPASS), .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, - .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL, + .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, - .idlest_reg = OMAP3430_CM_IDLEST_PLL, + .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, - .bypass_clk = &dpll2_fck, .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, @@ -356,15 +342,12 @@ static struct dpll_data dpll2_dd = { static struct clk dpll2_ck = { .name = "dpll2_ck", + .ops = &clkops_noncore_dpll_ops, .parent = &sys_ck, - .prcm_mod = OMAP3430_IVA2_MOD, .dpll_data = &dpll2_dd, - .flags = CLOCK_IN_OMAP343X | RECALC_ON_ENABLE, - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm = { .name = "dpll2_clkdm" }, + .clkdm_name = "dpll2_clkdm", .recalc = &omap3_dpll_recalc, }; @@ -379,14 +362,14 @@ static const struct clksel div16_dpll2_m2x2_clksel[] = { */ static struct clk dpll2_m2_ck = { .name = "dpll2_m2_ck", + .ops = &clkops_null, .parent = &dpll2_ck, - .prcm_mod = OMAP3430_IVA2_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_CM_CLKSEL2_PLL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, + OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll2_m2x2_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll2_clkdm" }, + .clkdm_name = "dpll2_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -396,20 +379,21 @@ static struct clk dpll2_m2_ck = { * REVISIT: Also supports fast relock bypass - not included below */ static struct dpll_data dpll3_dd = { - .mult_div1_reg = CM_CLKSEL1, + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, - .control_reg = CM_CLKEN, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, - .autoidle_reg = CM_AUTOIDLE, + .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, - .idlest_reg = CM_IDLEST, + .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, - .bypass_clk = &sys_ck, .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, @@ -418,15 +402,26 @@ static struct dpll_data dpll3_dd = { static struct clk dpll3_ck = { .name = "dpll3_ck", + .ops = &clkops_null, .parent = &sys_ck, - .prcm_mod = PLL_MOD, .dpll_data = &dpll3_dd, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | RECALC_ON_ENABLE, .round_rate = &omap2_dpll_round_rate, - .clkdm = { .name = "dpll3_clkdm" }, + .clkdm_name = "dpll3_clkdm", .recalc = &omap3_dpll_recalc, }; +/* + * This virtual clock provides the CLKOUTX2 output from the DPLL if the + * DPLL isn't bypassed + */ +static struct clk dpll3_x2_ck = { + .name = "dpll3_x2_ck", + .ops = &clkops_null, + .parent = &dpll3_ck, + .clkdm_name = "dpll3_clkdm", + .recalc = &omap3_clkoutx2_recalc, +}; + static const struct clksel_rate div31_dpll3_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, { .div = 2, .val = 2, .flags = RATE_IN_343X }, @@ -470,14 +465,13 @@ static const struct clksel div31_dpll3m2_clksel[] = { /* DPLL3 output M2 - primary control point for CORE speed */ static struct clk dpll3_m2_ck = { .name = "dpll3_m2_ck", + .ops = &clkops_null, .parent = &dpll3_ck, - .prcm_mod = PLL_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, .clksel = div31_dpll3m2_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll3_clkdm" }, + .clkdm_name = "dpll3_clkdm", .round_rate = &omap2_clksel_round_rate, .set_rate = &omap3_core_dpll_m2_set_rate, .recalc = &omap2_clksel_recalc, @@ -485,18 +479,17 @@ static struct clk dpll3_m2_ck = { static struct clk core_ck = { .name = "core_ck", + .ops = &clkops_null, .parent = &dpll3_m2_ck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, .recalc = &followparent_recalc, }; static struct clk dpll3_m2x2_ck = { .name = "dpll3_m2x2_ck", - .parent = &dpll3_m2_ck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll3_clkdm" }, - .recalc = &omap3_clkoutx2_recalc, + .ops = &clkops_null, + .parent = &dpll3_x2_ck, + .clkdm_name = "dpll3_clkdm", + .recalc = &followparent_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ @@ -508,34 +501,33 @@ static const struct clksel div16_dpll3_clksel[] = { /* This virtual clock is the source for dpll3_m3x2_ck */ static struct clk dpll3_m3_ck = { .name = "dpll3_m3_ck", + .ops = &clkops_null, .parent = &dpll3_ck, - .prcm_mod = OMAP3430_EMU_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL3_MASK, .clksel = div16_dpll3_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll3_clkdm" }, + .clkdm_name = "dpll3_clkdm", .recalc = &omap2_clksel_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll3_m3x2_ck = { .name = "dpll3_m3x2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll3_m3_ck, - .prcm_mod = PLL_MOD, - .enable_reg = CM_CLKEN, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, - .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE, - .clkdm = { .name = "dpll3_clkdm" }, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll3_clkdm", .recalc = &omap3_clkoutx2_recalc, }; static struct clk emu_core_alwon_ck = { .name = "emu_core_alwon_ck", + .ops = &clkops_null, .parent = &dpll3_m3x2_ck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll3_clkdm" }, + .clkdm_name = "dpll3_clkdm", .recalc = &followparent_recalc, }; @@ -543,21 +535,22 @@ static struct clk emu_core_alwon_ck = { /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ /* Type: DPLL */ static struct dpll_data dpll4_dd = { - .mult_div1_reg = CM_CLKSEL2, + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, - .control_reg = CM_CLKEN, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, - .autoidle_reg = CM_AUTOIDLE, + .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, - .idlest_reg = CM_IDLEST, + .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .bypass_clk = &sys_ck, .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, @@ -566,18 +559,28 @@ static struct dpll_data dpll4_dd = { static struct clk dpll4_ck = { .name = "dpll4_ck", + .ops = &clkops_noncore_dpll_ops, .parent = &sys_ck, - .prcm_mod = PLL_MOD, .dpll_data = &dpll4_dd, - .flags = CLOCK_IN_OMAP343X | RECALC_ON_ENABLE, - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm = { .name = "dpll4_clkdm" }, + .set_rate = &omap3_dpll4_set_rate, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_dpll_recalc, }; +/* + * This virtual clock provides the CLKOUTX2 output from the DPLL if the + * DPLL isn't bypassed -- + * XXX does this serve any downstream clocks? + */ +static struct clk dpll4_x2_ck = { + .name = "dpll4_x2_ck", + .ops = &clkops_null, + .parent = &dpll4_ck, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap3_clkoutx2_recalc, +}; + static const struct clksel div16_dpll4_clksel[] = { { .parent = &dpll4_ck, .rates = div16_dpll_rates }, { .parent = NULL } @@ -586,26 +589,25 @@ static const struct clksel div16_dpll4_clksel[] = { /* This virtual clock is the source for dpll4_m2x2_ck */ static struct clk dpll4_m2_ck = { .name = "dpll4_m2_ck", + .ops = &clkops_null, .parent = &dpll4_ck, - .prcm_mod = PLL_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_CM_CLKSEL3, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), .clksel_mask = OMAP3430_DIV_96M_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll4_clkdm" }, + .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m2x2_ck = { .name = "dpll4_m2x2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m2_ck, - .prcm_mod = PLL_MOD, - .enable_reg = CM_CLKEN, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_96M_SHIFT, - .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE, - .clkdm = { .name = "dpll4_clkdm" }, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -617,17 +619,15 @@ static struct clk dpll4_m2x2_ck = { */ static struct clk omap_96m_alwon_fck = { .name = "omap_96m_alwon_fck", + .ops = &clkops_null, .parent = &dpll4_m2x2_ck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "prm_clkdm" }, .recalc = &followparent_recalc, }; static struct clk cm_96m_fck = { .name = "cm_96m_fck", + .ops = &clkops_null, .parent = &omap_96m_alwon_fck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, .recalc = &followparent_recalc, }; @@ -649,41 +649,38 @@ static const struct clksel omap_96m_fck_clksel[] = { static struct clk omap_96m_fck = { .name = "omap_96m_fck", + .ops = &clkops_null, .parent = &sys_ck, - .prcm_mod = PLL_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_96M_MASK, .clksel = omap_96m_fck_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, .recalc = &omap2_clksel_recalc, }; /* This virtual clock is the source for dpll4_m3x2_ck */ static struct clk dpll4_m3_ck = { .name = "dpll4_m3_ck", + .ops = &clkops_null, .parent = &dpll4_ck, - .prcm_mod = OMAP3430_DSS_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_TV_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll4_clkdm" }, + .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m3x2_ck = { .name = "dpll4_m3x2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m3_ck, - .prcm_mod = PLL_MOD, .init = &omap2_init_clksel_parent, - .enable_reg = CM_CLKEN, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_TV_SHIFT, - .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE, - .clkdm = { .name = "dpll4_clkdm" }, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -705,13 +702,11 @@ static const struct clksel omap_54m_clksel[] = { static struct clk omap_54m_fck = { .name = "omap_54m_fck", - .prcm_mod = PLL_MOD, + .ops = &clkops_null, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_54M_MASK, .clksel = omap_54m_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -733,36 +728,32 @@ static const struct clksel omap_48m_clksel[] = { static struct clk omap_48m_fck = { .name = "omap_48m_fck", - .prcm_mod = PLL_MOD, + .ops = &clkops_null, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_48M_MASK, .clksel = omap_48m_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, .recalc = &omap2_clksel_recalc, }; static struct clk omap_12m_fck = { .name = "omap_12m_fck", + .ops = &clkops_null, .parent = &omap_48m_fck, .fixed_div = 4, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, .recalc = &omap2_fixed_divisor_recalc, }; /* This virstual clock is the source for dpll4_m4x2_ck */ static struct clk dpll4_m4_ck = { .name = "dpll4_m4_ck", + .ops = &clkops_null, .parent = &dpll4_ck, - .prcm_mod = OMAP3430_DSS_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll4_clkdm" }, + .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, .set_rate = &omap2_clksel_set_rate, .round_rate = &omap2_clksel_round_rate, @@ -771,73 +762,71 @@ static struct clk dpll4_m4_ck = { /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m4x2_ck = { .name = "dpll4_m4x2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m4_ck, - .prcm_mod = PLL_MOD, - .enable_reg = CM_CLKEN, - .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT, - .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE, - .clkdm = { .name = "dpll4_clkdm" }, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; /* This virtual clock is the source for dpll4_m5x2_ck */ static struct clk dpll4_m5_ck = { .name = "dpll4_m5_ck", + .ops = &clkops_null, .parent = &dpll4_ck, - .prcm_mod = OMAP3430_CAM_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll4_clkdm" }, + .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m5x2_ck = { .name = "dpll4_m5x2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m5_ck, - .prcm_mod = PLL_MOD, - .enable_reg = CM_CLKEN, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, - .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE, - .clkdm = { .name = "dpll4_clkdm" }, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; /* This virtual clock is the source for dpll4_m6x2_ck */ static struct clk dpll4_m6_ck = { .name = "dpll4_m6_ck", + .ops = &clkops_null, .parent = &dpll4_ck, - .prcm_mod = OMAP3430_EMU_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL4_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll4_clkdm" }, + .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m6x2_ck = { .name = "dpll4_m6x2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m6_ck, - .prcm_mod = PLL_MOD, .init = &omap2_init_clksel_parent, - .enable_reg = CM_CLKEN, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, - .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE, - .clkdm = { .name = "dpll4_clkdm" }, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; static struct clk emu_per_alwon_ck = { .name = "emu_per_alwon_ck", + .ops = &clkops_null, .parent = &dpll4_m6x2_ck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll4_clkdm" }, + .clkdm_name = "dpll4_clkdm", .recalc = &followparent_recalc, }; @@ -846,21 +835,22 @@ static struct clk emu_per_alwon_ck = { /* Type: DPLL */ /* 3430ES2 only */ static struct dpll_data dpll5_dd = { - .mult_div1_reg = OMAP3430ES2_CM_CLKSEL4, + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, - .control_reg = OMAP3430ES2_CM_CLKEN2, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, - .autoidle_reg = OMAP3430ES2_CM_AUTOIDLE2_PLL, + .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, - .idlest_reg = CM_IDLEST2, + .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, - .bypass_clk = &sys_ck, .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, @@ -869,15 +859,12 @@ static struct dpll_data dpll5_dd = { static struct clk dpll5_ck = { .name = "dpll5_ck", + .ops = &clkops_noncore_dpll_ops, .parent = &sys_ck, - .prcm_mod = PLL_MOD, .dpll_data = &dpll5_dd, - .flags = CLOCK_IN_OMAP3430ES2 | RECALC_ON_ENABLE, - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm = { .name = "dpll5_clkdm" }, + .clkdm_name = "dpll5_clkdm", .recalc = &omap3_dpll_recalc, }; @@ -888,14 +875,13 @@ static const struct clksel div16_dpll5_clksel[] = { static struct clk dpll5_m2_ck = { .name = "dpll5_m2_ck", + .ops = &clkops_null, .parent = &dpll5_ck, - .prcm_mod = PLL_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430ES2_CM_CLKSEL5, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), .clksel_mask = OMAP3430ES2_DIV_120M_MASK, .clksel = div16_dpll5_clksel, - .flags = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "dpll5_clkdm" }, + .clkdm_name = "dpll5_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -931,15 +917,14 @@ static const struct clksel clkout2_src_clksel[] = { static struct clk clkout2_src_ck = { .name = "clkout2_src_ck", - .prcm_mod = OMAP3430_CCR_MOD, + .ops = &clkops_omap2_dflt, .init = &omap2_init_clksel_parent, - .enable_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET, + .enable_reg = OMAP3430_CM_CLKOUT_CTRL, .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, - .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET, + .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, .clksel = clkout2_src_clksel, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "cm_clkdm" }, + .clkdm_name = "core_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -959,13 +944,11 @@ static const struct clksel sys_clkout2_clksel[] = { static struct clk sys_clkout2 = { .name = "sys_clkout2", - .prcm_mod = OMAP3430_CCR_MOD, + .ops = &clkops_null, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET, + .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, .clksel = sys_clkout2_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -973,9 +956,8 @@ static struct clk sys_clkout2 = { static struct clk corex2_fck = { .name = "corex2_fck", + .ops = &clkops_null, .parent = &dpll3_m2x2_ck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, .recalc = &followparent_recalc, }; @@ -993,24 +975,26 @@ static const struct clksel div4_core_clksel[] = { { .parent = NULL } }; +/* + * REVISIT: Are these in DPLL power domain or CM power domain? docs + * may be inconsistent here? + */ static struct clk dpll1_fck = { .name = "dpll1_fck", + .ops = &clkops_null, .parent = &core_ck, - .prcm_mod = MPU_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_CM_CLKSEL1_PLL, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, .clksel = div4_core_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, .recalc = &omap2_clksel_recalc, }; static struct clk mpu_ck = { .name = "mpu_ck", + .ops = &clkops_null, .parent = &dpll1_x2m2_ck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "mpu_clkdm" }, + .clkdm_name = "mpu_clkdm", .recalc = &followparent_recalc, }; @@ -1028,14 +1012,12 @@ static const struct clksel arm_fck_clksel[] = { static struct clk arm_fck = { .name = "arm_fck", + .ops = &clkops_null, .parent = &mpu_ck, - .prcm_mod = MPU_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_CM_IDLEST_PLL, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, .clksel = arm_fck_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "mpu_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1047,34 +1029,30 @@ static struct clk arm_fck = { */ static struct clk emu_mpu_alwon_ck = { .name = "emu_mpu_alwon_ck", + .ops = &clkops_null, .parent = &mpu_ck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "mpu_clkdm" }, .recalc = &followparent_recalc, }; static struct clk dpll2_fck = { .name = "dpll2_fck", + .ops = &clkops_null, .parent = &core_ck, - .prcm_mod = OMAP3430_IVA2_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_CM_CLKSEL1_PLL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, .clksel = div4_core_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, .recalc = &omap2_clksel_recalc, }; static struct clk iva2_ck = { .name = "iva2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll2_m2_ck, - .prcm_mod = OMAP3430_IVA2_MOD, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "iva2_clkdm" }, + .clkdm_name = "iva2_clkdm", .recalc = &followparent_recalc, }; @@ -1087,14 +1065,13 @@ static const struct clksel div2_core_clksel[] = { static struct clk l3_ick = { .name = "l3_ick", + .ops = &clkops_null, .parent = &core_ck, - .prcm_mod = CORE_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L3_MASK, .clksel = div2_core_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "core_l3_clkdm" }, + .clkdm_name = "core_l3_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1105,14 +1082,13 @@ static const struct clksel div2_l3_clksel[] = { static struct clk l4_ick = { .name = "l4_ick", + .ops = &clkops_null, .parent = &l3_ick, - .prcm_mod = CORE_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L4_MASK, .clksel = div2_l3_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1124,14 +1100,12 @@ static const struct clksel div2_l4_clksel[] = { static struct clk rm_ick = { .name = "rm_ick", + .ops = &clkops_null, .parent = &l4_ick, - .prcm_mod = WKUP_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_RM_MASK, .clksel = div2_l4_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "cm_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1147,56 +1121,53 @@ static const struct clksel gfx_l3_clksel[] = { /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ static struct clk gfx_l3_ck = { .name = "gfx_l3_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &l3_ick, - .prcm_mod = GFX_MOD, .init = &omap2_init_clksel_parent, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), .enable_bit = OMAP_EN_GFX_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, - .clkdm = { .name = "gfx_3430es1_clkdm" }, .recalc = &followparent_recalc, }; static struct clk gfx_l3_fck = { .name = "gfx_l3_fck", + .ops = &clkops_null, .parent = &gfx_l3_ck, - .prcm_mod = GFX_MOD, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_mask = OMAP_CLKSEL_GFX_MASK, .clksel = gfx_l3_clksel, - .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "gfx_3430es1_clkdm" }, + .clkdm_name = "gfx_3430es1_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gfx_l3_ick = { .name = "gfx_l3_ick", + .ops = &clkops_null, .parent = &gfx_l3_ck, - .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "gfx_3430es1_clkdm" }, + .clkdm_name = "gfx_3430es1_clkdm", .recalc = &followparent_recalc, }; static struct clk gfx_cg1_ck = { .name = "gfx_cg1_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &gfx_l3_fck, /* REVISIT: correct? */ - .prcm_mod = GFX_MOD, - .enable_reg = CM_FCLKEN, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES1_EN_2D_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, - .clkdm = { .name = "gfx_3430es1_clkdm" }, + .clkdm_name = "gfx_3430es1_clkdm", .recalc = &followparent_recalc, }; static struct clk gfx_cg2_ck = { .name = "gfx_cg2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &gfx_l3_fck, /* REVISIT: correct? */ - .prcm_mod = GFX_MOD, - .enable_reg = CM_FCLKEN, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES1_EN_3D_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, - .clkdm = { .name = "gfx_3430es1_clkdm" }, + .clkdm_name = "gfx_3430es1_clkdm", .recalc = &followparent_recalc, }; @@ -1222,26 +1193,25 @@ static const struct clksel sgx_clksel[] = { static struct clk sgx_fck = { .name = "sgx_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, - .prcm_mod = OMAP3430ES2_SGX_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, .clksel = sgx_clksel, - .flags = CLOCK_IN_OMAP3430ES2, - .clkdm = { .name = "sgx_clkdm" }, + .clkdm_name = "sgx_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk sgx_ick = { .name = "sgx_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l3_ick, - .prcm_mod = OMAP3430ES2_SGX_MOD, - .enable_reg = CM_ICLKEN, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, - .clkdm = { .name = "sgx_clkdm" }, + .clkdm_name = "sgx_clkdm", .recalc = &followparent_recalc, }; @@ -1249,12 +1219,12 @@ static struct clk sgx_ick = { static struct clk d2d_26m_fck = { .name = "d2d_26m_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, - .clkdm = { .name = "d2d_clkdm" }, + .clkdm_name = "d2d_clkdm", .recalc = &followparent_recalc, }; @@ -1266,68 +1236,56 @@ static const struct clksel omap343x_gpt_clksel[] = { static struct clk gpt10_fck = { .name = "gpt10_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, - .prcm_mod = CORE_MOD, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_GPT10_SHIFT, - .idlest_bit = OMAP3430_ST_GPT10_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt11_fck = { .name = "gpt11_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, - .prcm_mod = CORE_MOD, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_GPT11_SHIFT, - .idlest_bit = OMAP3430_ST_GPT11_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk cpefuse_fck = { .name = "cpefuse_fck", + .ops = &clkops_omap2_dflt, .parent = &sys_ck, - .prcm_mod = CORE_MOD, - .enable_reg = OMAP3430ES2_CM_FCLKEN3, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, - .idlest_bit = OMAP3430ES2_ST_CPEFUSE_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "cm_clkdm" }, .recalc = &followparent_recalc, }; static struct clk ts_fck = { .name = "ts_fck", + .ops = &clkops_omap2_dflt, .parent = &omap_32k_fck, - .prcm_mod = CORE_MOD, - .enable_reg = OMAP3430ES2_CM_FCLKEN3, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_TS_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; static struct clk usbtll_fck = { .name = "usbtll_fck", + .ops = &clkops_omap2_dflt, .parent = &dpll5_m2_ck, - .prcm_mod = CORE_MOD, - .enable_reg = OMAP3430ES2_CM_FCLKEN3, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, - .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1335,98 +1293,84 @@ static struct clk usbtll_fck = { static struct clk core_96m_fck = { .name = "core_96m_fck", + .ops = &clkops_null, .parent = &omap_96m_fck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mmchs3_fck = { .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &core_96m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, - .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mmchs2_fck = { .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_96m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, - .idlest_bit = OMAP3430_ST_MMC2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mspro_fck = { .name = "mspro_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_96m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, - .idlest_bit = OMAP3430_ST_MSPRO_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mmchs1_fck = { .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_96m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, - .idlest_bit = OMAP3430_ST_MMC1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk i2c3_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &core_96m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C3_SHIFT, - .idlest_bit = OMAP3430_ST_I2C3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk i2c2_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &core_96m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C2_SHIFT, - .idlest_bit = OMAP3430_ST_I2C2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk i2c1_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_96m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C1_SHIFT, - .idlest_bit = OMAP3430_ST_I2C1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1450,154 +1394,108 @@ static const struct clksel mcbsp_15_clksel[] = { { .parent = NULL } }; -static struct clk mcbsp5_src_fck = { - .name = "mcbsp_src_fck", +static struct clk mcbsp5_fck = { + .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 5, - .prcm_mod = CLK_REG_IN_SCM, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP343X_CONTROL_DEVCONF1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, .clksel = mcbsp_15_clksel, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; -static struct clk mcbsp5_fck = { +static struct clk mcbsp1_fck = { .name = "mcbsp_fck", - .id = 5, - .parent = &mcbsp5_src_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, - .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, - .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp1_src_fck = { - .name = "mcbsp_src_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, - .prcm_mod = CLK_REG_IN_SCM, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP2_CONTROL_DEVCONF0, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, .clksel = mcbsp_15_clksel, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; -static struct clk mcbsp1_fck = { - .name = "mcbsp_fck", - .id = 1, - .parent = &mcbsp1_src_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, - .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, - .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .recalc = &followparent_recalc, -}; - /* CORE_48M_FCK-derived clocks */ static struct clk core_48m_fck = { .name = "core_48m_fck", + .ops = &clkops_null, .parent = &omap_48m_fck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcspi4_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 4, .parent = &core_48m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, - .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; static struct clk mcspi3_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &core_48m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, - .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; static struct clk mcspi2_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &core_48m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, - .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; static struct clk mcspi1_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_48m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, - .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; static struct clk uart2_fck = { .name = "uart2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_48m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, - .idlest_bit = OMAP3430_ST_UART2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; static struct clk uart1_fck = { .name = "uart1_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_48m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, - .idlest_bit = OMAP3430_ST_UART1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; -/* XXX doublecheck: is this idle or standby? */ static struct clk fshostusb_fck = { .name = "fshostusb_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_48m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, - .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1605,21 +1503,18 @@ static struct clk fshostusb_fck = { static struct clk core_12m_fck = { .name = "core_12m_fck", + .ops = &clkops_null, .parent = &omap_12m_fck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk hdq_fck = { .name = "hdq_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_12m_fck, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, - .idlest_bit = OMAP3430_ST_HDQ_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1640,51 +1535,24 @@ static const struct clksel ssi_ssr_clksel[] = { { .parent = NULL } }; -static struct clk ssi_ssr_fck_3430es1 = { +static struct clk ssi_ssr_fck = { .name = "ssi_ssr_fck", + .ops = &clkops_omap2_dflt, .init = &omap2_init_clksel_parent, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, .clksel = ssi_ssr_clksel, - .flags = CLOCK_IN_OMAP3430ES1, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; -static struct clk ssi_ssr_fck_3430es2 = { - .name = "ssi_ssr_fck", - .init = &omap2_init_clksel_parent, - .prcm_mod = CORE_MOD, - .enable_reg = CM_FCLKEN1, - .enable_bit = OMAP3430_EN_SSI_SHIFT, - .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT, - .clksel_reg = CM_CLKSEL, - .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, - .clksel = ssi_ssr_clksel, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .recalc = &omap2_clksel_recalc, -}; - -/* It's unfortunate that we need to duplicate this clock. */ -static struct clk ssi_sst_fck_3430es1 = { +static struct clk ssi_sst_fck = { .name = "ssi_sst_fck", - .parent = &ssi_ssr_fck_3430es1, + .ops = &clkops_null, + .parent = &ssi_ssr_fck, .fixed_div = 2, - .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "core_l4_clkdm" }, - .recalc = &omap2_fixed_divisor_recalc, -}; - -static struct clk ssi_sst_fck_3430es2 = { - .name = "ssi_sst_fck", - .parent = &ssi_ssr_fck_3430es2, - .fixed_div = 2, - .flags = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &omap2_fixed_divisor_recalc, }; @@ -1698,53 +1566,40 @@ static struct clk ssi_sst_fck_3430es2 = { */ static struct clk core_l3_ick = { .name = "core_l3_ick", + .ops = &clkops_null, .parent = &l3_ick, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "core_l3_clkdm" }, + .init = &omap2_init_clk_clkdm, + .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; -static struct clk hsotgusb_ick_3430es1 = { +static struct clk hsotgusb_ick = { .name = "hsotgusb_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, - .clkdm = { .name = "core_l3_clkdm" }, - .recalc = &followparent_recalc, -}; - -static struct clk hsotgusb_ick_3430es2 = { - .name = "hsotgusb_ick", - .parent = &core_l3_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, - .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, - .idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "core_l3_clkdm" }, + .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; static struct clk sdrc_ick = { .name = "sdrc_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SDRC_SHIFT, - .idlest_bit = OMAP3430_ST_SDRC_SHIFT, - .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY, - .clkdm = { .name = "core_l3_clkdm" }, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; static struct clk gpmc_fck = { .name = "gpmc_fck", + .ops = &clkops_null, .parent = &core_l3_ick, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | - ENABLE_ON_INIT, - .clkdm = { .name = "core_l3_clkdm" }, + .flags = ENABLE_ON_INIT, /* huh? */ + .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; @@ -1752,21 +1607,17 @@ static struct clk gpmc_fck = { static struct clk security_l3_ick = { .name = "security_l3_ick", + .ops = &clkops_null, .parent = &l3_ick, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "core_l3_clkdm" }, .recalc = &followparent_recalc, }; static struct clk pka_ick = { .name = "pka_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &security_l3_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_PKA_SHIFT, - .idlest_bit = OMAP3430_ST_PKA_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l3_clkdm" }, .recalc = &followparent_recalc, }; @@ -1774,333 +1625,282 @@ static struct clk pka_ick = { static struct clk core_l4_ick = { .name = "core_l4_ick", + .ops = &clkops_null, .parent = &l4_ick, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "core_l4_clkdm" }, + .init = &omap2_init_clk_clkdm, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk usbtll_ick = { .name = "usbtll_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN3, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, - .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mmchs3_ick = { .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, - .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; /* Intersystem Communication Registers - chassis mode only */ static struct clk icr_ick = { .name = "icr_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_ICR_SHIFT, - .idlest_bit = OMAP3430_ST_ICR_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk aes2_ick = { .name = "aes2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_AES2_SHIFT, - .idlest_bit = OMAP3430_ST_AES2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk sha12_ick = { .name = "sha12_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SHA12_SHIFT, - .idlest_bit = OMAP3430_ST_SHA12_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk des2_ick = { .name = "des2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_DES2_SHIFT, - .idlest_bit = OMAP3430_ST_DES2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mmchs2_ick = { .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, - .idlest_bit = OMAP3430_ST_MMC2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mmchs1_ick = { .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, - .idlest_bit = OMAP3430_ST_MMC1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mspro_ick = { .name = "mspro_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, - .idlest_bit = OMAP3430_ST_MSPRO_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk hdq_ick = { .name = "hdq_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, - .idlest_bit = OMAP3430_ST_HDQ_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcspi4_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 4, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, - .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcspi3_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, - .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcspi2_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, - .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcspi1_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, - .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk i2c3_ick = { .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C3_SHIFT, - .idlest_bit = OMAP3430_ST_I2C3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk i2c2_ick = { .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C2_SHIFT, - .idlest_bit = OMAP3430_ST_I2C2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk i2c1_ick = { .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C1_SHIFT, - .idlest_bit = OMAP3430_ST_I2C1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk uart2_ick = { .name = "uart2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, - .idlest_bit = OMAP3430_ST_UART2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk uart1_ick = { .name = "uart1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, - .idlest_bit = OMAP3430_ST_UART1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt11_ick = { .name = "gpt11_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT11_SHIFT, - .idlest_bit = OMAP3430_ST_GPT11_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt10_ick = { .name = "gpt10_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT10_SHIFT, - .idlest_bit = OMAP3430_ST_GPT10_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcbsp5_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 5, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, - .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcbsp1_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, - .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk fac_ick = { .name = "fac_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, - .idlest_bit = OMAP3430ES1_ST_FAC_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mailboxes_ick = { .name = "mailboxes_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, - .idlest_bit = OMAP3430_ST_MAILBOXES_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk omapctrl_ick = { .name = "omapctrl_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, - .idlest_bit = OMAP3430_ST_OMAPCTRL_SHIFT, - .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, + .flags = ENABLE_ON_INIT, .recalc = &followparent_recalc, }; @@ -2108,39 +1908,25 @@ static struct clk omapctrl_ick = { static struct clk ssi_l4_ick = { .name = "ssi_l4_ick", + .ops = &clkops_null, .parent = &l4_ick, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; -static struct clk ssi_ick_3430es1 = { +static struct clk ssi_ick = { .name = "ssi_ick", + .ops = &clkops_omap2_dflt, .parent = &ssi_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; -static struct clk ssi_ick_3430es2 = { - .name = "ssi_ick", - .parent = &ssi_l4_ick, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN1, - .enable_bit = OMAP3430_EN_SSI_SHIFT, - .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, - .recalc = &followparent_recalc, -}; +/* REVISIT: Technically the TRM claims that this is CORE_CLK based, + * but l4_ick makes more sense to me */ -/* - * REVISIT: Technically the TRM claims that this is CORE_CLK based, - * but l4_ick makes more sense to me - */ static const struct clksel usb_l4_clksel[] = { { .parent = &l4_ick, .rates = div2_rates }, { .parent = NULL }, @@ -2148,17 +1934,14 @@ static const struct clksel usb_l4_clksel[] = { static struct clk usb_l4_ick = { .name = "usb_l4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ick, - .prcm_mod = CORE_MOD, .init = &omap2_init_clksel_parent, - .enable_reg = CM_ICLKEN1, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, - .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, .clksel = usb_l4_clksel, - .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2168,140 +1951,100 @@ static struct clk usb_l4_ick = { static struct clk security_l4_ick2 = { .name = "security_l4_ick2", + .ops = &clkops_null, .parent = &l4_ick, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; static struct clk aes1_ick = { .name = "aes1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &security_l4_ick2, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_AES1_SHIFT, - .idlest_bit = OMAP3430_ST_AES1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; static struct clk rng_ick = { .name = "rng_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &security_l4_ick2, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_RNG_SHIFT, - .idlest_bit = OMAP3430_ST_RNG_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; static struct clk sha11_ick = { .name = "sha11_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &security_l4_ick2, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_SHA11_SHIFT, - .idlest_bit = OMAP3430_ST_SHA11_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; static struct clk des1_ick = { .name = "des1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &security_l4_ick2, - .prcm_mod = CORE_MOD, - .enable_reg = CM_ICLKEN2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_DES1_SHIFT, - .idlest_bit = OMAP3430_ST_DES1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; /* DSS */ -static struct clk dss1_alwon_fck_3430es1 = { +static struct clk dss1_alwon_fck = { .name = "dss1_alwon_fck", + .ops = &clkops_omap2_dflt, .parent = &dpll4_m4x2_ck, - .prcm_mod = OMAP3430_DSS_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS1_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, - .clkdm = { .name = "dss_clkdm" }, - .recalc = &followparent_recalc, -}; - -static struct clk dss1_alwon_fck_3430es2 = { - .name = "dss1_alwon_fck", - .parent = &dpll4_m4x2_ck, - .init = &omap2_init_clksel_parent, - .prcm_mod = OMAP3430_DSS_MOD, - .enable_reg = CM_FCLKEN, - .enable_bit = OMAP3430_EN_DSS1_SHIFT, - .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "dss_clkdm" }, + .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; static struct clk dss_tv_fck = { .name = "dss_tv_fck", + .ops = &clkops_omap2_dflt, .parent = &omap_54m_fck, - .prcm_mod = OMAP3430_DSS_MOD, - .enable_reg = CM_FCLKEN, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_TV_SHIFT, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */ + .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; static struct clk dss_96m_fck = { .name = "dss_96m_fck", + .ops = &clkops_omap2_dflt, .parent = &omap_96m_fck, - .prcm_mod = OMAP3430_DSS_MOD, - .enable_reg = CM_FCLKEN, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_TV_SHIFT, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "dss_clkdm" }, + .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; static struct clk dss2_alwon_fck = { .name = "dss2_alwon_fck", + .ops = &clkops_omap2_dflt, .parent = &sys_ck, - .prcm_mod = OMAP3430_DSS_MOD, - .enable_reg = CM_FCLKEN, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS2_SHIFT, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "dss_clkdm" }, + .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; -static struct clk dss_ick_3430es1 = { +static struct clk dss_ick = { /* Handles both L3 and L4 clocks */ .name = "dss_ick", + .ops = &clkops_omap2_dflt, .parent = &l4_ick, - .prcm_mod = OMAP3430_DSS_MOD, - .enable_reg = CM_ICLKEN, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, - .clkdm = { .name = "dss_clkdm" }, - .recalc = &followparent_recalc, -}; - -static struct clk dss_ick_3430es2 = { - /* Handles both L3 and L4 clocks */ - .name = "dss_ick", - .parent = &l4_ick, - .prcm_mod = OMAP3430_DSS_MOD, - .enable_reg = CM_ICLKEN, - .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, - .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "dss_clkdm" }, + .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; @@ -2309,35 +2052,34 @@ static struct clk dss_ick_3430es2 = { static struct clk cam_mclk = { .name = "cam_mclk", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m5x2_ck, - .prcm_mod = OMAP3430_CAM_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "cam_clkdm" }, + .clkdm_name = "cam_clkdm", .recalc = &followparent_recalc, }; static struct clk cam_ick = { /* Handles both L3 and L4 clocks */ .name = "cam_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ick, - .prcm_mod = OMAP3430_CAM_MOD, - .enable_reg = CM_ICLKEN, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "cam_clkdm" }, + .clkdm_name = "cam_clkdm", .recalc = &followparent_recalc, }; static struct clk csi2_96m_fck = { .name = "csi2_96m_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_96m_fck, - .prcm_mod = OMAP3430_CAM_MOD, - .enable_reg = CM_FCLKEN, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_CSI2_SHIFT, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "cam_clkdm" }, + .clkdm_name = "cam_clkdm", .recalc = &followparent_recalc, }; @@ -2345,37 +2087,35 @@ static struct clk csi2_96m_fck = { static struct clk usbhost_120m_fck = { .name = "usbhost_120m_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll5_m2_ck, - .prcm_mod = OMAP3430ES2_USBHOST_MOD, - .enable_reg = CM_FCLKEN, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, - .clkdm = { .name = "usbhost_clkdm" }, + .clkdm_name = "usbhost_clkdm", .recalc = &followparent_recalc, }; static struct clk usbhost_48m_fck = { .name = "usbhost_48m_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &omap_48m_fck, - .prcm_mod = OMAP3430ES2_USBHOST_MOD, - .enable_reg = CM_FCLKEN, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, - .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "usbhost_clkdm" }, + .clkdm_name = "usbhost_clkdm", .recalc = &followparent_recalc, }; static struct clk usbhost_ick = { /* Handles both L3 and L4 clocks */ .name = "usbhost_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ick, - .prcm_mod = OMAP3430ES2_USBHOST_MOD, - .enable_reg = CM_ICLKEN, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, - .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "usbhost_clkdm" }, + .clkdm_name = "usbhost_clkdm", .recalc = &followparent_recalc, }; @@ -2407,156 +2147,137 @@ static const struct clksel usim_clksel[] = { /* 3430ES2 only */ static struct clk usim_fck = { .name = "usim_fck", - .prcm_mod = WKUP_MOD, + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, - .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, .clksel = usim_clksel, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, .recalc = &omap2_clksel_recalc, }; /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ static struct clk gpt1_fck = { .name = "gpt1_fck", - .prcm_mod = WKUP_MOD, + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT1_SHIFT, - .idlest_bit = OMAP3430_ST_GPT1_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk wkup_32k_fck = { .name = "wkup_32k_fck", + .ops = &clkops_null, + .init = &omap2_init_clk_clkdm, .parent = &omap_32k_fck, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio1_dbck = { .name = "gpio1_dbck", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_32k_fck, - .prcm_mod = WKUP_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, - .idlest_bit = OMAP3430_ST_GPIO1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk wdt2_fck = { .name = "wdt2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_32k_fck, - .prcm_mod = WKUP_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, - .idlest_bit = OMAP3430_ST_WDT2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk wkup_l4_ick = { .name = "wkup_l4_ick", + .ops = &clkops_null, .parent = &sys_ck, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; +/* 3430ES2 only */ +/* Never specifically named in the TRM, so we have to infer a likely name */ static struct clk usim_ick = { .name = "usim_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, - .prcm_mod = WKUP_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, - .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk wdt2_ick = { .name = "wdt2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, - .prcm_mod = WKUP_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, - .idlest_bit = OMAP3430_ST_WDT2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk wdt1_ick = { .name = "wdt1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, - .prcm_mod = WKUP_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT1_SHIFT, - .idlest_bit = OMAP3430_ST_WDT1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio1_ick = { .name = "gpio1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, - .prcm_mod = WKUP_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, - .idlest_bit = OMAP3430_ST_GPIO1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk omap_32ksync_ick = { .name = "omap_32ksync_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, - .prcm_mod = WKUP_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, - .idlest_bit = OMAP3430_ST_32KSYNC_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; +/* XXX This clock no longer exists in 3430 TRM rev F */ static struct clk gpt12_ick = { .name = "gpt12_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, - .prcm_mod = WKUP_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT12_SHIFT, - .idlest_bit = OMAP3430_ST_GPT12_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt1_ick = { .name = "gpt1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, - .prcm_mod = WKUP_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT1_SHIFT, - .idlest_bit = OMAP3430_ST_GPT1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, + .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2566,456 +2287,392 @@ static struct clk gpt1_ick = { static struct clk per_96m_fck = { .name = "per_96m_fck", + .ops = &clkops_null, .parent = &omap_96m_alwon_fck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "per_clkdm" }, + .init = &omap2_init_clk_clkdm, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk per_48m_fck = { .name = "per_48m_fck", + .ops = &clkops_null, .parent = &omap_48m_fck, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "per_clkdm" }, + .init = &omap2_init_clk_clkdm, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk uart3_fck = { .name = "uart3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_48m_fck, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, - .idlest_bit = OMAP3430_ST_UART3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt2_fck = { .name = "gpt2_fck", - .prcm_mod = OMAP3430_PER_MOD, + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT2_SHIFT, - .idlest_bit = OMAP3430_ST_GPT2_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt3_fck = { .name = "gpt3_fck", - .prcm_mod = OMAP3430_PER_MOD, + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT3_SHIFT, - .idlest_bit = OMAP3430_ST_GPT3_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt4_fck = { .name = "gpt4_fck", - .prcm_mod = OMAP3430_PER_MOD, + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT4_SHIFT, - .idlest_bit = OMAP3430_ST_GPT4_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt5_fck = { .name = "gpt5_fck", - .prcm_mod = OMAP3430_PER_MOD, + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT5_SHIFT, - .idlest_bit = OMAP3430_ST_GPT5_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt6_fck = { .name = "gpt6_fck", - .prcm_mod = OMAP3430_PER_MOD, + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT6_SHIFT, - .idlest_bit = OMAP3430_ST_GPT6_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt7_fck = { .name = "gpt7_fck", - .prcm_mod = OMAP3430_PER_MOD, + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT7_SHIFT, - .idlest_bit = OMAP3430_ST_GPT7_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt8_fck = { .name = "gpt8_fck", - .prcm_mod = OMAP3430_PER_MOD, + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT8_SHIFT, - .idlest_bit = OMAP3430_ST_GPT8_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt9_fck = { .name = "gpt9_fck", - .prcm_mod = OMAP3430_PER_MOD, + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT9_SHIFT, - .idlest_bit = OMAP3430_ST_GPT9_SHIFT, - .clksel_reg = CM_CLKSEL, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk per_32k_alwon_fck = { .name = "per_32k_alwon_fck", + .ops = &clkops_null, .parent = &omap_32k_fck, - .clkdm = { .name = "per_clkdm" }, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio6_dbck = { .name = "gpio6_dbck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, - .idlest_bit = OMAP3430_ST_GPIO6_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio5_dbck = { .name = "gpio5_dbck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, - .idlest_bit = OMAP3430_ST_GPIO5_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio4_dbck = { .name = "gpio4_dbck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, - .idlest_bit = OMAP3430_ST_GPIO4_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio3_dbck = { .name = "gpio3_dbck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, - .idlest_bit = OMAP3430_ST_GPIO3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio2_dbck = { .name = "gpio2_dbck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, - .idlest_bit = OMAP3430_ST_GPIO2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk wdt3_fck = { .name = "wdt3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, - .idlest_bit = OMAP3430_ST_WDT3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk per_l4_ick = { .name = "per_l4_ick", + .ops = &clkops_null, .parent = &l4_ick, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio6_ick = { .name = "gpio6_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, - .idlest_bit = OMAP3430_ST_GPIO6_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio5_ick = { .name = "gpio5_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, - .idlest_bit = OMAP3430_ST_GPIO5_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio4_ick = { .name = "gpio4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, - .idlest_bit = OMAP3430_ST_GPIO4_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio3_ick = { .name = "gpio3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, - .idlest_bit = OMAP3430_ST_GPIO3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio2_ick = { .name = "gpio2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, - .idlest_bit = OMAP3430_ST_GPIO2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk wdt3_ick = { .name = "wdt3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, - .idlest_bit = OMAP3430_ST_WDT3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk uart3_ick = { .name = "uart3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, - .idlest_bit = OMAP3430_ST_UART3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt9_ick = { .name = "gpt9_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT9_SHIFT, - .idlest_bit = OMAP3430_ST_GPT9_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt8_ick = { .name = "gpt8_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT8_SHIFT, - .idlest_bit = OMAP3430_ST_GPT8_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt7_ick = { .name = "gpt7_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT7_SHIFT, - .idlest_bit = OMAP3430_ST_GPT7_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt6_ick = { .name = "gpt6_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT6_SHIFT, - .idlest_bit = OMAP3430_ST_GPT6_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt5_ick = { .name = "gpt5_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT5_SHIFT, - .idlest_bit = OMAP3430_ST_GPT5_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt4_ick = { .name = "gpt4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT4_SHIFT, - .idlest_bit = OMAP3430_ST_GPT4_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt3_ick = { .name = "gpt3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT3_SHIFT, - .idlest_bit = OMAP3430_ST_GPT3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt2_ick = { .name = "gpt2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT2_SHIFT, - .idlest_bit = OMAP3430_ST_GPT2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk mcbsp2_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, - .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk mcbsp3_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, - .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk mcbsp4_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 4, .parent = &per_l4_ick, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_ICLKEN, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, - .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -3025,81 +2682,45 @@ static const struct clksel mcbsp_234_clksel[] = { { .parent = NULL } }; -static struct clk mcbsp2_src_fck = { - .name = "mcbsp_src_fck", - .id = 2, - .prcm_mod = CLK_REG_IN_SCM, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP2_CONTROL_DEVCONF0, - .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, - .clksel = mcbsp_234_clksel, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "per_clkdm" }, - .recalc = &omap2_clksel_recalc, -}; - static struct clk mcbsp2_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, - .parent = &mcbsp2_src_fck, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_FCLKEN, - .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, - .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp3_src_fck = { - .name = "mcbsp_src_fck", - .id = 3, - .prcm_mod = CLK_REG_IN_SCM, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP343X_CONTROL_DEVCONF1, - .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, .clksel = mcbsp_234_clksel, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp3_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 3, - .parent = &mcbsp3_src_fck, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_FCLKEN, - .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, - .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp4_src_fck = { - .name = "mcbsp_src_fck", - .id = 4, - .prcm_mod = CLK_REG_IN_SCM, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP343X_CONTROL_DEVCONF1, - .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, .clksel = mcbsp_234_clksel, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "per_clkdm" }, + .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp4_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 4, - .parent = &mcbsp4_src_fck, - .prcm_mod = OMAP3430_PER_MOD, - .enable_reg = CM_FCLKEN, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, - .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "per_clkdm" }, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, + .clksel = mcbsp_234_clksel, + .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3142,13 +2763,12 @@ static const struct clksel emu_src_clksel[] = { */ static struct clk emu_src_ck = { .name = "emu_src_ck", - .prcm_mod = OMAP3430_EMU_MOD, + .ops = &clkops_null, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_MUX_CTRL_MASK, .clksel = emu_src_clksel, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "emu_clkdm" }, + .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3167,13 +2787,12 @@ static const struct clksel pclk_emu_clksel[] = { static struct clk pclk_fck = { .name = "pclk_fck", - .prcm_mod = OMAP3430_EMU_MOD, + .ops = &clkops_null, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, .clksel = pclk_emu_clksel, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "emu_clkdm" }, + .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3191,13 +2810,12 @@ static const struct clksel pclkx2_emu_clksel[] = { static struct clk pclkx2_fck = { .name = "pclkx2_fck", - .prcm_mod = OMAP3430_EMU_MOD, + .ops = &clkops_null, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, .clksel = pclkx2_emu_clksel, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "emu_clkdm" }, + .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3208,25 +2826,23 @@ static const struct clksel atclk_emu_clksel[] = { static struct clk atclk_fck = { .name = "atclk_fck", - .prcm_mod = OMAP3430_EMU_MOD, + .ops = &clkops_null, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, .clksel = atclk_emu_clksel, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "emu_clkdm" }, + .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk traceclk_src_fck = { .name = "traceclk_src_fck", - .prcm_mod = OMAP3430_EMU_MOD, + .ops = &clkops_null, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, .clksel = emu_src_clksel, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "emu_clkdm" }, + .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3244,13 +2860,12 @@ static const struct clksel traceclk_clksel[] = { static struct clk traceclk_fck = { .name = "traceclk_fck", - .prcm_mod = OMAP3430_EMU_MOD, + .ops = &clkops_null, .init = &omap2_init_clksel_parent, - .clksel_reg = CM_CLKSEL1, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, .clksel = traceclk_clksel, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "emu_clkdm" }, + .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3259,277 +2874,46 @@ static struct clk traceclk_fck = { /* SmartReflex fclk (VDD1) */ static struct clk sr1_fck = { .name = "sr1_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, - .prcm_mod = WKUP_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR1_SHIFT, - .idlest_bit = OMAP3430_ST_SR1_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, .recalc = &followparent_recalc, }; /* SmartReflex fclk (VDD2) */ static struct clk sr2_fck = { .name = "sr2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, - .prcm_mod = WKUP_MOD, - .enable_reg = CM_FCLKEN, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR2_SHIFT, - .idlest_bit = OMAP3430_ST_SR2_SHIFT, - .flags = CLOCK_IN_OMAP343X | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, .recalc = &followparent_recalc, }; static struct clk sr_l4_ick = { .name = "sr_l4_ick", + .ops = &clkops_null, /* RMK: missing? */ .parent = &l4_ick, - .flags = CLOCK_IN_OMAP343X, - .clkdm = { .name = "core_l4_clkdm" }, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; /* SECURE_32K_FCK clocks */ -/* XXX Make sure idlest_bit/wait_ready with no enable_bit works */ +/* XXX This clock no longer exists in 3430 TRM rev F */ static struct clk gpt12_fck = { .name = "gpt12_fck", + .ops = &clkops_null, .parent = &secure_32k_fck, - .idlest_bit = OMAP3430_ST_GPT12_SHIFT, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | WAIT_READY, - .clkdm = { .name = "prm_clkdm" }, .recalc = &followparent_recalc, }; static struct clk wdt1_fck = { .name = "wdt1_fck", + .ops = &clkops_null, .parent = &secure_32k_fck, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm = { .name = "prm_clkdm" }, - .recalc = &followparent_recalc, -}; - -static struct clk *onchip_34xx_clks[] __initdata = { - &omap_32k_fck, - &virt_12m_ck, - &virt_13m_ck, - &virt_16_8m_ck, - &virt_19_2m_ck, - &virt_26m_ck, - &virt_38_4m_ck, - &osc_sys_ck, - &sys_ck, - &sys_altclk, - &mcbsp_clks, - &sys_clkout1, - &dpll1_ck, - &dpll1_x2_ck, - &dpll1_x2m2_ck, - &dpll2_ck, - &dpll2_m2_ck, - &dpll3_ck, - &core_ck, - &dpll3_m2_ck, - &dpll3_m2x2_ck, - &dpll3_m3_ck, - &dpll3_m3x2_ck, - &emu_core_alwon_ck, - &dpll4_ck, - &omap_96m_alwon_fck, - &omap_96m_fck, - &cm_96m_fck, - &omap_54m_fck, - &omap_48m_fck, - &omap_12m_fck, - &dpll4_m2_ck, - &dpll4_m2x2_ck, - &dpll4_m3_ck, - &dpll4_m3x2_ck, - &dpll4_m4_ck, - &dpll4_m4x2_ck, - &dpll4_m5_ck, - &dpll4_m5x2_ck, - &dpll4_m6_ck, - &dpll4_m6x2_ck, - &emu_per_alwon_ck, - &dpll5_ck, - &dpll5_m2_ck, - &clkout2_src_ck, - &sys_clkout2, - &corex2_fck, - &dpll1_fck, - &mpu_ck, - &arm_fck, - &emu_mpu_alwon_ck, - &dpll2_fck, - &iva2_ck, - &l3_ick, - &l4_ick, - &rm_ick, - &gfx_l3_ck, - &gfx_l3_fck, - &gfx_l3_ick, - &gfx_cg1_ck, - &gfx_cg2_ck, - &sgx_fck, - &sgx_ick, - &d2d_26m_fck, - &gpt10_fck, - &gpt11_fck, - &cpefuse_fck, - &ts_fck, - &usbtll_fck, - &core_96m_fck, - &mmchs3_fck, - &mmchs2_fck, - &mspro_fck, - &mmchs1_fck, - &i2c3_fck, - &i2c2_fck, - &i2c1_fck, - &mcbsp5_src_fck, - &mcbsp5_fck, - &mcbsp1_src_fck, - &mcbsp1_fck, - &core_48m_fck, - &mcspi4_fck, - &mcspi3_fck, - &mcspi2_fck, - &mcspi1_fck, - &uart2_fck, - &uart1_fck, - &fshostusb_fck, - &core_12m_fck, - &hdq_fck, - &ssi_ssr_fck_3430es1, - &ssi_ssr_fck_3430es2, - &ssi_sst_fck_3430es1, - &ssi_sst_fck_3430es2, - &core_l3_ick, - &hsotgusb_ick_3430es1, - &hsotgusb_ick_3430es2, - &sdrc_ick, - &gpmc_fck, - &security_l3_ick, - &pka_ick, - &core_l4_ick, - &usbtll_ick, - &mmchs3_ick, - &icr_ick, - &aes2_ick, - &sha12_ick, - &des2_ick, - &mmchs2_ick, - &mmchs1_ick, - &mspro_ick, - &hdq_ick, - &mcspi4_ick, - &mcspi3_ick, - &mcspi2_ick, - &mcspi1_ick, - &i2c3_ick, - &i2c2_ick, - &i2c1_ick, - &uart2_ick, - &uart1_ick, - &gpt11_ick, - &gpt10_ick, - &mcbsp5_ick, - &mcbsp1_ick, - &fac_ick, - &mailboxes_ick, - &omapctrl_ick, - &ssi_l4_ick, - &ssi_ick_3430es1, - &ssi_ick_3430es2, - &usb_l4_ick, - &security_l4_ick2, - &aes1_ick, - &rng_ick, - &sha11_ick, - &des1_ick, - &dss1_alwon_fck_3430es1, - &dss1_alwon_fck_3430es2, - &dss_tv_fck, - &dss_96m_fck, - &dss2_alwon_fck, - &dss_ick_3430es1, - &dss_ick_3430es2, - &cam_mclk, - &cam_ick, - &csi2_96m_fck, - &usbhost_120m_fck, - &usbhost_48m_fck, - &usbhost_ick, - &usim_fck, - &gpt1_fck, - &wkup_32k_fck, - &gpio1_dbck, - &wdt2_fck, - &wkup_l4_ick, - &usim_ick, - &wdt2_ick, - &wdt1_ick, - &gpio1_ick, - &omap_32ksync_ick, - &gpt12_ick, - &gpt1_ick, - &per_96m_fck, - &per_48m_fck, - &uart3_fck, - &gpt2_fck, - &gpt3_fck, - &gpt4_fck, - &gpt5_fck, - &gpt6_fck, - &gpt7_fck, - &gpt8_fck, - &gpt9_fck, - &per_32k_alwon_fck, - &gpio6_dbck, - &gpio5_dbck, - &gpio4_dbck, - &gpio3_dbck, - &gpio2_dbck, - &wdt3_fck, - &per_l4_ick, - &gpio6_ick, - &gpio5_ick, - &gpio4_ick, - &gpio3_ick, - &gpio2_ick, - &wdt3_ick, - &uart3_ick, - &gpt9_ick, - &gpt8_ick, - &gpt7_ick, - &gpt6_ick, - &gpt5_ick, - &gpt4_ick, - &gpt3_ick, - &gpt2_ick, - &mcbsp2_ick, - &mcbsp3_ick, - &mcbsp4_ick, - &mcbsp2_src_fck, - &mcbsp2_fck, - &mcbsp3_src_fck, - &mcbsp3_fck, - &mcbsp4_src_fck, - &mcbsp4_fck, - &emu_src_ck, - &pclk_fck, - &pclkx2_fck, - &atclk_fck, - &traceclk_src_fck, - &traceclk_fck, - &sr1_fck, - &sr2_fck, - &sr_l4_ick, - &secure_32k_fck, - &gpt12_fck, - &wdt1_fck, + .recalc = &followparent_recalc, }; #endif diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index f713d0b9cbc..0e7d501865b 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -22,6 +22,7 @@ #include #include #include +#include #include @@ -73,14 +74,11 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep) pwrdm = pwrdm_lookup(autodep->pwrdm.name); if (!pwrdm) { - pr_debug("clockdomain: _autodep_lookup: powerdomain %s " - "does not exist\n", autodep->pwrdm.name); - WARN_ON(1); - return; + pr_err("clockdomain: autodeps: powerdomain %s does not exist\n", + autodep->pwrdm.name); + pwrdm = ERR_PTR(-ENOENT); } autodep->pwrdm.ptr = pwrdm; - - return; } /* @@ -96,6 +94,9 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm) struct clkdm_pwrdm_autodep *autodep; for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) { + if (IS_ERR(autodep->pwrdm.ptr)) + continue; + if (!omap_chip_is(autodep->omap_chip)) continue; @@ -121,6 +122,9 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm) struct clkdm_pwrdm_autodep *autodep; for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) { + if (IS_ERR(autodep->pwrdm.ptr)) + continue; + if (!omap_chip_is(autodep->omap_chip)) continue; @@ -204,8 +208,8 @@ int clkdm_register(struct clockdomain *clkdm) pwrdm = pwrdm_lookup(clkdm->pwrdm.name); if (!pwrdm) { - pr_debug("clockdomain: clkdm_register %s: powerdomain %s " - "does not exist\n", clkdm->name, clkdm->pwrdm.name); + pr_err("clockdomain: %s: powerdomain %s does not exist\n", + clkdm->name, clkdm->pwrdm.name); return -EINVAL; } clkdm->pwrdm.ptr = pwrdm; @@ -215,7 +219,7 @@ int clkdm_register(struct clockdomain *clkdm) if (_clkdm_lookup(clkdm->name)) { ret = -EEXIST; goto cr_unlock; - }; + } list_add(&clkdm->node, &clkdm_list); diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h index a21df93a07f..281d5da1918 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains.h @@ -21,6 +21,13 @@ * sys_clkout/sys_clkout2. */ +/* This is an implicit clockdomain - it is never defined as such in TRM */ +static struct clockdomain wkup_clkdm = { + .name = "wkup_clkdm", + .pwrdm = { .name = "wkup_pwrdm" }, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), +}; + static struct clockdomain prm_clkdm = { .name = "prm_clkdm", .pwrdm = { .name = "wkup_pwrdm" }, @@ -33,16 +40,6 @@ static struct clockdomain cm_clkdm = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), }; -/* - * virt_opp_clkdm is intended solely for use with virtual OPP clocks, - * e.g., virt_prcm_set, until OPP handling is rationalized. - */ -static struct clockdomain virt_opp_clkdm = { - .name = "virt_opp_clkdm", - .pwrdm = { .name = "wkup_pwrdm" }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), -}; - /* * 2420-only clockdomains */ @@ -319,9 +316,9 @@ static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { static struct clockdomain *clockdomains_omap[] = { + &wkup_clkdm, &cm_clkdm, &prm_clkdm, - &virt_opp_clkdm, #ifdef CONFIG_ARCH_OMAP2420 &mpu_2420_clkdm, diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index a9a0df522ca..297a2fe634e 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -147,7 +147,6 @@ /* CM_IDLEST3_CORE */ /* 2430 only */ -#define OMAP2430_ST_SDRC_SHIFT 2 #define OMAP2430_ST_SDRC_MASK (1 << 2) /* CM_IDLEST4_CORE */ diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index 7750becd5d3..65fdf78c91e 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -16,24 +16,29 @@ #include "prcm-common.h" +#ifndef __ASSEMBLER__ +#define OMAP_CM_REGADDR(module, reg) \ + IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg)) +#else #define OMAP2420_CM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) #define OMAP2430_CM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) #define OMAP34XX_CM_REGADDR(module, reg) \ IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) +#endif /* * Architecture-specific global CM registers - * Use __raw_{read,write}l() with these registers. + * Use cm_{read,write}_reg() with these registers. * These registers appear once per CM module. */ -#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) -#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) -#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) +#define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000) +#define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010) +#define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c) -#define OMAP3430_CM_CLKOUT_CTRL_OFFSET 0x0070 +#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) /* * Module specific CM registers from CM_BASE + domain offset @@ -62,6 +67,7 @@ #define CM_CLKSEL2 0x0044 #define CM_CLKSTCTRL 0x0048 + /* Architecture-specific registers */ #define OMAP24XX_CM_FCLKEN2 0x0004 diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 2568b0c24d6..3d4482c996c 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -181,6 +181,7 @@ static inline void omap_init_mbox(void) mbox_device.num_resources = ARRAY_SIZE(omap3_mbox_resources); mbox_device.resource = omap3_mbox_resources; } else { + pr_err("%s: platform not supported\n", __func__); return; } platform_device_register(&mbox_device); @@ -477,11 +478,12 @@ static void __init omap_hsmmc_reset(void) } dummy_pdev.id = i; - iclk = clk_get(dev, "mmchs_ick"); + dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); + iclk = clk_get(dev, "ick"); if (iclk && clk_enable(iclk)) iclk = NULL; - fclk = clk_get(dev, "mmchs_fck"); + fclk = clk_get(dev, "fck"); if (fclk && clk_enable(fclk)) fclk = NULL; diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index adbe21fcd68..916fcd3a232 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -23,6 +23,7 @@ #include #include + #include #include #include diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 2842fe8dc36..9ba20d985dd 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -157,26 +157,6 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG); } -int omap_irq_pending(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { - struct omap_irq_bank *bank = irq_banks + i; - int irq; - - for (irq = 0; irq < bank->nr_irqs; irq += IRQ_BITS_PER_REG) { - int offset = irq & (~(IRQ_BITS_PER_REG - 1)); - - if (intc_bank_read_reg(bank, (INTC_PENDING_IRQ0 + - offset))) - return 1; - } - } - - return 0; -} - void __init omap_init_irq(void) { unsigned long nr_of_irqs = 0; diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 544dde9d07b..fd5b8a5925c 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -1,7 +1,7 @@ /* * Mailbox reservation modules for OMAP2/3 * - * Copyright (C) 2006-2008 Nokia Corporation + * Copyright (C) 2006-2009 Nokia Corporation * Written by: Hiroshi DOYU * and Paul Mundt * @@ -18,8 +18,6 @@ #include #include -#define DRV_NAME "omap2-mailbox" - #define MAILBOX_REVISION 0x000 #define MAILBOX_SYSCONFIG 0x010 #define MAILBOX_SYSSTATUS 0x014 @@ -27,12 +25,13 @@ #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u)) -#define MAILBOX_IRQENABLE(u) (0x108 + 8 * (u)) +#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u)) #define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u))) #define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1)) #define MBOX_REG_SIZE 0x120 +#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32)) static void __iomem *mbox_base; @@ -49,7 +48,7 @@ struct omap_mbox2_priv { unsigned long irqstatus; u32 newmsg_bit; u32 notfull_bit; - char ctx[MBOX_REG_SIZE]; + u32 ctx[MBOX_NR_REGS]; }; static struct clk *mbox_ick_handle; @@ -175,13 +174,11 @@ static void omap2_mbox_save_ctx(struct omap_mbox *mbox) int i; struct omap_mbox2_priv *p = mbox->priv; - for (i = 0; i < MBOX_REG_SIZE; i += sizeof(u32)) { - u32 val; - - val = mbox_read_reg(i); - *(u32 *)(p->ctx + i) = val; + for (i = 0; i < MBOX_NR_REGS; i++) { + p->ctx[i] = mbox_read_reg(i * sizeof(u32)); - dev_dbg(mbox->dev, "%s\t[%02d] %08x\n", __func__, i, val); + dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__, + i, p->ctx[i]); } } @@ -190,13 +187,11 @@ static void omap2_mbox_restore_ctx(struct omap_mbox *mbox) int i; struct omap_mbox2_priv *p = mbox->priv; - for (i = 0; i < MBOX_REG_SIZE; i += sizeof(u32)) { - u32 val; + for (i = 0; i < MBOX_NR_REGS; i++) { + mbox_write_reg(p->ctx[i], i * sizeof(u32)); - val = *(u32 *)(p->ctx + i); - mbox_write_reg(val, i); - - dev_dbg(mbox->dev, "%s\t[%02d] %08x\n", __func__, i, val); + dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__, + i, p->ctx[i]); } } @@ -287,13 +282,12 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) return -ENOMEM; /* DSP or IVA2 IRQ */ - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (unlikely(!res)) { + mbox_dsp_info.irq = platform_get_irq(pdev, 0); + if (mbox_dsp_info.irq < 0) { dev_err(&pdev->dev, "invalid irq resource\n"); ret = -ENODEV; goto err_dsp; } - mbox_dsp_info.irq = res->start; ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info); if (ret) @@ -337,7 +331,7 @@ static struct platform_driver omap2_mbox_driver = { .probe = omap2_mbox_probe, .remove = __devexit_p(omap2_mbox_remove), .driver = { - .name = DRV_NAME, + .name = "omap2-mailbox", }, }; @@ -357,4 +351,4 @@ module_exit(omap2_mbox_exit); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions"); MODULE_AUTHOR("Hiroshi DOYU , Paul Mundt"); -MODULE_ALIAS("platform:"DRV_NAME); +MODULE_ALIAS("platform:omap2-mailbox"); diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index a9e631fc113..a5c0f0435cd 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -24,8 +24,6 @@ #include #include -const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" }; - static void omap2_mcbsp2_mux_setup(void) { omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); @@ -57,8 +55,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, .ops = &omap2_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 2, }, { .phys_base = OMAP24XX_MCBSP2_BASE, @@ -67,8 +63,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, .ops = &omap2_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 2, }, }; #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) @@ -86,8 +80,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, .ops = &omap2_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 2, }, { .phys_base = OMAP24XX_MCBSP2_BASE, @@ -96,8 +88,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, .ops = &omap2_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 2, }, { .phys_base = OMAP2430_MCBSP3_BASE, @@ -106,8 +96,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, .ops = &omap2_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 2, }, { .phys_base = OMAP2430_MCBSP4_BASE, @@ -116,8 +104,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, .ops = &omap2_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 2, }, { .phys_base = OMAP2430_MCBSP5_BASE, @@ -126,8 +112,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, .ops = &omap2_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 2, }, }; #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) @@ -145,8 +129,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, .ops = &omap2_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 2, }, { .phys_base = OMAP34XX_MCBSP2_BASE, @@ -155,8 +137,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, .ops = &omap2_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 2, }, { .phys_base = OMAP34XX_MCBSP3_BASE, @@ -165,8 +145,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, .ops = &omap2_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 2, }, { .phys_base = OMAP34XX_MCBSP4_BASE, @@ -175,8 +153,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, .ops = &omap2_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 2, }, { .phys_base = OMAP34XX_MCBSP5_BASE, @@ -185,8 +161,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, .ops = &omap2_mcbsp_ops, - .clk_names = clk_names, - .num_clks = 2, }, }; #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c deleted file mode 100644 index b00f5f4dfe4..00000000000 --- a/arch/arm/mach-omap2/pm-debug.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/pm_debug.c - * - * OMAP Power Management debug routines - * - * Copyright (C) 2005 Texas Instruments, Inc. - * Copyright (C) 2006-2008 Nokia Corporation - * - * Written by: - * Richard Woodruff - * Tony Lindgren - * Juha Yrjola - * Amit Kucheria - * Igor Stoppa - * Jouni Hogander - * - * Based on pm.c for omap2 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include - -#include "prm.h" -#include "cm.h" -#include "pm.h" - -#ifdef CONFIG_PM_DEBUG -int omap2_pm_debug = 0; - -#define DUMP_PRM_MOD_REG(mod, reg) \ - regs[reg_count].name = #mod "." #reg; \ - regs[reg_count++].val = prm_read_mod_reg(mod, reg) -#define DUMP_CM_MOD_REG(mod, reg) \ - regs[reg_count].name = #mod "." #reg; \ - regs[reg_count++].val = cm_read_mod_reg(mod, reg) -#define DUMP_PRM_REG(reg) \ - regs[reg_count].name = #reg; \ - regs[reg_count++].val = __raw_readl(reg) -#define DUMP_CM_REG(reg) \ - regs[reg_count].name = #reg; \ - regs[reg_count++].val = __raw_readl(reg) -#define DUMP_INTC_REG(reg, off) \ - regs[reg_count].name = #reg; \ - regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off))) - -void omap2_pm_dump(int mode, int resume, unsigned int us) -{ - struct reg { - const char *name; - u32 val; - } regs[32]; - int reg_count = 0, i; - const char *s1 = NULL, *s2 = NULL; - - if (!resume) { -#if 0 - /* MPU */ - DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET); - DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL); - DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL); - DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST); - DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP); -#endif -#if 0 - /* INTC */ - DUMP_INTC_REG(INTC_MIR0, 0x0084); - DUMP_INTC_REG(INTC_MIR1, 0x00a4); - DUMP_INTC_REG(INTC_MIR2, 0x00c4); -#endif -#if 0 - DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1); - if (cpu_is_omap24xx()) { - DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2); - DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD, - OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET); - DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD, - OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET); - } - DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN); - DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1); - DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2); - DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN); - DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN); - DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE); - DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST); -#endif -#if 0 - /* DSP */ - if (cpu_is_omap24xx()) { - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN); - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN); - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST); - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE); - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL); - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST); - } -#endif - } else { - DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1); - if (cpu_is_omap24xx()) - DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2); - DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST); - DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET); -#if 1 - DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098); - DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8); - DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8); -#endif - } - - switch (mode) { - case 0: - s1 = "full"; - s2 = "retention"; - break; - case 1: - s1 = "MPU"; - s2 = "retention"; - break; - case 2: - s1 = "MPU"; - s2 = "idle"; - break; - } - - if (!resume) -#if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ) - printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2, - jiffies_to_msecs(get_next_timer_interrupt(jiffies) - - jiffies)); -#else - printk("--- Going to %s %s\n", s1, s2); -#endif - else - printk("--- Woke up (slept for %u.%03u ms)\n", - us / 1000, us % 1000); - - for (i = 0; i < reg_count; i++) - printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val); -} - -#endif diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 4652136de15..ea8ceaed09c 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -1,18 +1,13 @@ /* * linux/arch/arm/mach-omap2/pm.c * - * OMAP Power Management Common Routines + * OMAP2 Power Management Routines * - * Copyright (C) 2005 Texas Instruments, Inc. - * Copyright (C) 2006-2008 Nokia Corporation + * Copyright (C) 2006 Nokia Corporation + * Tony Lindgren * - * Written by: + * Copyright (C) 2005 Texas Instruments, Inc. * Richard Woodruff - * Tony Lindgren - * Juha Yrjola - * Amit Kucheria - * Igor Stoppa - * Jouni Hogander * * Based on pm.c for omap1 * @@ -22,98 +17,95 @@ */ #include -#include - -#include -#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include #include +#include +#include +#include +#include +#include #include -#include "pm.h" -unsigned short enable_dyn_sleep; -unsigned short clocks_off_while_idle; -atomic_t sleep_block = ATOMIC_INIT(0); +static struct clk *vclk; +static void (*omap2_sram_idle)(void); +static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev); +static void (*saved_idle)(void); -static ssize_t idle_show(struct kobject *, struct kobj_attribute *, char *); -static ssize_t idle_store(struct kobject *k, struct kobj_attribute *, - const char *buf, size_t n); +extern void __init pmdomain_init(void); +extern void pmdomain_set_autoidle(void); -static struct kobj_attribute sleep_while_idle_attr = - __ATTR(sleep_while_idle, 0644, idle_show, idle_store); - -static struct kobj_attribute clocks_off_while_idle_attr = - __ATTR(clocks_off_while_idle, 0644, idle_show, idle_store); - -static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr, - char *buf) -{ - if (attr == &sleep_while_idle_attr) - return sprintf(buf, "%hu\n", enable_dyn_sleep); - else if (attr == &clocks_off_while_idle_attr) - return sprintf(buf, "%hu\n", clocks_off_while_idle); - else - return -EINVAL; -} +static unsigned int omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_SIZE]; -static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr, - const char *buf, size_t n) +void omap2_pm_idle(void) { - unsigned short value; - - if (sscanf(buf, "%hu", &value) != 1 || - (value != 0 && value != 1)) { - printk(KERN_ERR "idle_store: Invalid value\n"); - return -EINVAL; + local_irq_disable(); + local_fiq_disable(); + if (need_resched()) { + local_fiq_enable(); + local_irq_enable(); + return; } - if (attr == &sleep_while_idle_attr) - enable_dyn_sleep = value; - else if (attr == &clocks_off_while_idle_attr) - clocks_off_while_idle = value; - else - return -EINVAL; + omap2_sram_idle(); + local_fiq_enable(); + local_irq_enable(); +} - return n; +static int omap2_pm_prepare(void) +{ + /* We cannot sleep in idle until we have resumed */ + saved_idle = pm_idle; + pm_idle = NULL; + return 0; } -void omap2_block_sleep(void) +static int omap2_pm_suspend(void) { - atomic_inc(&sleep_block); + return 0; } -void omap2_allow_sleep(void) +static int omap2_pm_enter(suspend_state_t state) { - int i; + int ret = 0; + + switch (state) + { + case PM_SUSPEND_STANDBY: + case PM_SUSPEND_MEM: + ret = omap2_pm_suspend(); + break; + default: + ret = -EINVAL; + } - i = atomic_dec_return(&sleep_block); - BUG_ON(i < 0); + return ret; } -static int __init omap_pm_init(void) +static void omap2_pm_finish(void) { - int error = -1; - - if (cpu_is_omap24xx()) - error = omap2_pm_init(); - if (cpu_is_omap34xx()) - error = omap3_pm_init(); - if (error) { - printk(KERN_ERR "omap2|3_pm_init failed: %d\n", error); - return error; - } + pm_idle = saved_idle; +} - /* disabled till drivers are fixed */ - enable_dyn_sleep = 0; - error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr); - if (error) - printk(KERN_ERR "sysfs_create_file failed: %d\n", error); - error = sysfs_create_file(power_kobj, - &clocks_off_while_idle_attr.attr); - if (error) - printk(KERN_ERR "sysfs_create_file failed: %d\n", error); - - return error; +static struct platform_suspend_ops omap_pm_ops = { + .prepare = omap2_pm_prepare, + .enter = omap2_pm_enter, + .finish = omap2_pm_finish, + .valid = suspend_valid_only_mem, +}; + +static int __init omap2_pm_init(void) +{ + return 0; } -late_initcall(omap_pm_init); +__initcall(omap2_pm_init); diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h deleted file mode 100644 index 468f9904827..00000000000 --- a/arch/arm/mach-omap2/pm.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef __ARCH_ARM_MACH_OMAP2_PM_H -#define __ARCH_ARM_MACH_OMAP2_PM_H -/* - * linux/arch/arm/mach-omap2/pm.h - * - * OMAP Power Management Routines - * - * Copyright (C) 2008 Nokia Corporation - * Jouni Hogander - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -extern int omap2_pm_init(void); -extern int omap3_pm_init(void); - -extern unsigned short enable_dyn_sleep; -extern unsigned short clocks_off_while_idle; -extern atomic_t sleep_block; - -extern void omap2_block_sleep(void); -extern void omap2_allow_sleep(void); - - -#ifdef CONFIG_PM_DEBUG -extern void omap2_pm_dump(int mode, int resume, unsigned int us); -extern int omap2_pm_debug; -#else -#define omap2_pm_dump(mode, resume, us) do {} while (0); -#define omap2_pm_debug 0 -#endif /* CONFIG_PM_DEBUG */ -#endif diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c deleted file mode 100644 index 90feb35937d..00000000000 --- a/arch/arm/mach-omap2/pm24xx.c +++ /dev/null @@ -1,560 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/pm.c - * - * OMAP2 Power Management Routines - * - * Copyright (C) 2005 Texas Instruments, Inc. - * Copyright (C) 2006-2008 Nokia Corporation - * - * Written by: - * Richard Woodruff - * Tony Lindgren - * Juha Yrjola - * Amit Kucheria - * Igor Stoppa - * - * Based on pm.c for omap1 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "prm.h" -#include "prm-regbits-24xx.h" -#include "cm.h" -#include "cm-regbits-24xx.h" -#include "sdrc.h" -#include "pm.h" - -#include -#include - -static void (*omap2_sram_idle)(void); -static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, - void __iomem *sdrc_power); -static void (*saved_idle)(void); - -static struct powerdomain *mpu_pwrdm; -static struct powerdomain *core_pwrdm; - -static struct clockdomain *dsp_clkdm; -static struct clockdomain *gfx_clkdm; - -static struct clk *osc_ck, *emul_ck; - -static int omap2_fclks_active(void) -{ - u32 f1, f2; - - f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); - - /* Ignore UART clocks. These are handled by UART core (serial.c) */ - f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2); - f2 &= ~OMAP24XX_EN_UART3; - - if (f1 | f2) - return 1; - return 0; -} - -static void omap2_enter_full_retention(void) -{ - u32 l; - struct timespec ts_preidle, ts_postidle, ts_idle; - - /* There is 1 reference hold for all children of the oscillator - * clock, the following will remove it. If no one else uses the - * oscillator itself it will be disabled if/when we enter retention - * mode. - */ - clk_disable(osc_ck); - - /* Clear old wake-up events */ - /* REVISIT: These write to reserved bits? */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); - - /* - * Set MPU powerdomain's next power state to RETENTION; - * preserve logic state during retention - */ - pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); - pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); - - /* Workaround to kill USB */ - l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; - omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); - - omap2_gpio_prepare_for_retention(); - - if (omap2_pm_debug) { - omap2_pm_dump(0, 0, 0); - getnstimeofday(&ts_preidle); - } - - /* One last check for pending IRQs to avoid extra latency due - * to sleeping unnecessarily. */ - if (omap_irq_pending()) - goto no_sleep; - - omap_uart_prepare_idle(0); - omap_uart_prepare_idle(1); - omap_uart_prepare_idle(2); - - /* Jump to SRAM suspend code */ - omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL), - OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL), - OMAP_SDRC_REGADDR(SDRC_POWER)); -no_sleep: - omap_uart_resume_idle(2); - omap_uart_resume_idle(1); - omap_uart_resume_idle(0); - - if (omap2_pm_debug) { - unsigned long long tmp; - - getnstimeofday(&ts_postidle); - ts_idle = timespec_sub(ts_postidle, ts_preidle); - tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; - omap2_pm_dump(0, 1, tmp); - } - omap2_gpio_resume_after_retention(); - - clk_enable(osc_ck); - - /* clear CORE wake-up events */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - - /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ - prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); - - /* MPU domain wake events */ - l = prm_read_mod_reg(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET); - if (l & 0x01) - prm_write_mod_reg(0x01, OCP_MOD, - OMAP2_PRM_IRQSTATUS_MPU_OFFSET); - if (l & 0x20) - prm_write_mod_reg(0x20, OCP_MOD, - OMAP2_PRM_IRQSTATUS_MPU_OFFSET); - - /* Mask future PRCM-to-MPU interrupts */ - prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET); -} - -static int omap2_i2c_active(void) -{ - u32 l; - - l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1); -} - -static int sti_console_enabled; - -static int omap2_allow_mpu_retention(void) -{ - u32 l; - - if (atomic_read(&sleep_block)) - return 0; - - /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ - l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 | - OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 | - OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1)) - return 0; - /* Check for UART3. */ - l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); - if (l & OMAP24XX_EN_UART3) - return 0; - if (sti_console_enabled) - return 0; - - return 1; -} - -static void omap2_enter_mpu_retention(void) -{ - int only_idle = 0; - struct timespec ts_preidle, ts_postidle, ts_idle; - - /* Putting MPU into the WFI state while a transfer is active - * seems to cause the I2C block to timeout. Why? Good question. */ - if (omap2_i2c_active()) - return; - - /* The peripherals seem not to be able to wake up the MPU when - * it is in retention mode. */ - if (omap2_allow_mpu_retention()) { - /* REVISIT: These write to reserved bits? */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); - - /* Try to enter MPU retention */ - prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | - OMAP_LOGICRETSTATE, - MPU_MOD, PM_PWSTCTRL); - } else { - /* Block MPU retention */ - - prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL); - only_idle = 1; - } - - if (omap2_pm_debug) { - omap2_pm_dump(only_idle ? 2 : 1, 0, 0); - getnstimeofday(&ts_preidle); - } - - omap2_sram_idle(); - - if (omap2_pm_debug) { - unsigned long long tmp; - - getnstimeofday(&ts_postidle); - ts_idle = timespec_sub(ts_postidle, ts_preidle); - tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; - omap2_pm_dump(only_idle ? 2 : 1, 1, tmp); - } -} - -static int omap2_can_sleep(void) -{ - if (!enable_dyn_sleep) - return 0; - if (omap2_fclks_active()) - return 0; - if (atomic_read(&sleep_block) > 0) - return 0; - if (osc_ck->usecount > 1) - return 0; - if (omap_dma_running()) - return 0; - - return 1; -} - -/* - * Note that you can use clock_event_device->min_delta_ns if you want to - * avoid reprogramming timer too often when using CONFIG_NO_HZ. - */ -static void omap2_pm_idle(void) -{ - local_irq_disable(); - local_fiq_disable(); - - if (!omap2_can_sleep()) { - if (!atomic_read(&sleep_block) && omap_irq_pending()) - goto out; - omap2_enter_mpu_retention(); - goto out; - } - - if (omap_irq_pending()) - goto out; - - omap2_enter_full_retention(); - -out: - local_fiq_enable(); - local_irq_enable(); -} - -static int omap2_pm_prepare(void) -{ - /* We cannot sleep in idle until we have resumed */ - saved_idle = pm_idle; - pm_idle = NULL; - - return 0; -} - -static int omap2_pm_suspend(void) -{ - u32 wken_wkup, mir1; - - wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); - prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN); - - /* Mask GPT1 */ - mir1 = omap_readl(0x480fe0a4); - omap_writel(1 << 5, 0x480fe0ac); - - omap_uart_prepare_suspend(); - omap2_enter_full_retention(); - - omap_writel(mir1, 0x480fe0a4); - prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); - - return 0; -} - -static int omap2_pm_enter(suspend_state_t state) -{ - int ret = 0; - - switch (state) { - case PM_SUSPEND_STANDBY: - case PM_SUSPEND_MEM: - ret = omap2_pm_suspend(); - break; - default: - ret = -EINVAL; - } - - return ret; -} - -static void omap2_pm_finish(void) -{ - pm_idle = saved_idle; -} - -static struct platform_suspend_ops omap_pm_ops = { - .prepare = omap2_pm_prepare, - .enter = omap2_pm_enter, - .finish = omap2_pm_finish, - .valid = suspend_valid_only_mem, -}; - -static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm) -{ - omap2_clkdm_allow_idle(clkdm); - return 0; -} - -static void __init prcm_setup_regs(void) -{ - int i, num_mem_banks; - struct powerdomain *pwrdm; - - /* Enable autoidle */ - prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD, - OMAP24XX_PRM_SYSCONFIG_OFFSET); - - /* Set all domain wakeup dependencies */ - prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP); - prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); - prm_write_mod_reg(0, CORE_MOD, PM_WKDEP); - if (cpu_is_omap2430()) - prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP); - - /* - * Set CORE powerdomain memory banks to retain their contents - * during RETENTION - */ - num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm); - for (i = 0; i < num_mem_banks; i++) - pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET); - - /* Set CORE powerdomain's next power state to RETENTION */ - pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); - - /* - * Set MPU powerdomain's next power state to RETENTION; - * preserve logic state during retention - */ - pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); - pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); - - /* Force-power down DSP, GFX powerdomains */ - - pwrdm = clkdm_get_pwrdm(dsp_clkdm); - pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); - omap2_clkdm_sleep(dsp_clkdm); - - pwrdm = clkdm_get_pwrdm(gfx_clkdm); - pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); - omap2_clkdm_sleep(gfx_clkdm); - - /* Enable clockdomain hardware-supervised control for all clkdms */ - clkdm_for_each(_pm_clkdm_enable_hwsup); - - /* Enable clock autoidle for all domains */ - cm_write_mod_reg(OMAP24XX_AUTO_CAM | - OMAP24XX_AUTO_MAILBOXES | - OMAP24XX_AUTO_WDT4 | - OMAP2420_AUTO_WDT3 | - OMAP24XX_AUTO_MSPRO | - OMAP2420_AUTO_MMC | - OMAP24XX_AUTO_FAC | - OMAP2420_AUTO_EAC | - OMAP24XX_AUTO_HDQ | - OMAP24XX_AUTO_UART2 | - OMAP24XX_AUTO_UART1 | - OMAP24XX_AUTO_I2C2 | - OMAP24XX_AUTO_I2C1 | - OMAP24XX_AUTO_MCSPI2 | - OMAP24XX_AUTO_MCSPI1 | - OMAP24XX_AUTO_MCBSP2 | - OMAP24XX_AUTO_MCBSP1 | - OMAP24XX_AUTO_GPT12 | - OMAP24XX_AUTO_GPT11 | - OMAP24XX_AUTO_GPT10 | - OMAP24XX_AUTO_GPT9 | - OMAP24XX_AUTO_GPT8 | - OMAP24XX_AUTO_GPT7 | - OMAP24XX_AUTO_GPT6 | - OMAP24XX_AUTO_GPT5 | - OMAP24XX_AUTO_GPT4 | - OMAP24XX_AUTO_GPT3 | - OMAP24XX_AUTO_GPT2 | - OMAP2420_AUTO_VLYNQ | - OMAP24XX_AUTO_DSS, - CORE_MOD, CM_AUTOIDLE1); - cm_write_mod_reg(OMAP24XX_AUTO_UART3 | - OMAP24XX_AUTO_SSI | - OMAP24XX_AUTO_USB, - CORE_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(OMAP24XX_AUTO_SDRC | - OMAP24XX_AUTO_GPMC | - OMAP24XX_AUTO_SDMA, - CORE_MOD, CM_AUTOIDLE3); - cm_write_mod_reg(OMAP24XX_AUTO_PKA | - OMAP24XX_AUTO_AES | - OMAP24XX_AUTO_RNG | - OMAP24XX_AUTO_SHA | - OMAP24XX_AUTO_DES, - CORE_MOD, OMAP24XX_CM_AUTOIDLE4); - - cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE); - - /* Put DPLL and both APLLs into autoidle mode */ - cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | - (0x03 << OMAP24XX_AUTO_96M_SHIFT) | - (0x03 << OMAP24XX_AUTO_54M_SHIFT), - PLL_MOD, CM_AUTOIDLE); - - cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL | - OMAP24XX_AUTO_WDT1 | - OMAP24XX_AUTO_MPU_WDT | - OMAP24XX_AUTO_GPIOS | - OMAP24XX_AUTO_32KSYNC | - OMAP24XX_AUTO_GPT1, - WKUP_MOD, CM_AUTOIDLE); - - /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk - * stabilisation */ - prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, - OMAP24XX_PRCM_CLKSSETUP_OFFSET); - - /* Configure automatic voltage transition */ - prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, - OMAP24XX_PRCM_VOLTSETUP_OFFSET); - prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT | - (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | - OMAP24XX_MEMRETCTRL | - (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | - (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), - OMAP24XX_GR_MOD, OMAP24XX_PRCM_VOLTCTRL_OFFSET); - - /* Enable wake-up events */ - prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1, - WKUP_MOD, PM_WKEN); -} - -int __init omap2_pm_init(void) -{ - u32 l; - - printk(KERN_INFO "Power Management for OMAP2 initializing\n"); - l = prm_read_mod_reg(OCP_MOD, OMAP24XX_PRM_REVISION_OFFSET); - printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); - - /* Look up important powerdomains, clockdomains */ - - mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); - if (!mpu_pwrdm) - pr_err("PM: mpu_pwrdm not found\n"); - - core_pwrdm = pwrdm_lookup("core_pwrdm"); - if (!core_pwrdm) - pr_err("PM: core_pwrdm not found\n"); - - dsp_clkdm = clkdm_lookup("dsp_clkdm"); - if (!dsp_clkdm) - pr_err("PM: mpu_clkdm not found\n"); - - gfx_clkdm = clkdm_lookup("gfx_clkdm"); - if (!gfx_clkdm) - pr_err("PM: gfx_clkdm not found\n"); - - - osc_ck = clk_get(NULL, "osc_ck"); - if (IS_ERR(osc_ck)) { - printk(KERN_ERR "could not get osc_ck\n"); - return -ENODEV; - } - - if (cpu_is_omap242x()) { - emul_ck = clk_get(NULL, "emul_ck"); - if (IS_ERR(emul_ck)) { - printk(KERN_ERR "could not get emul_ck\n"); - clk_put(osc_ck); - return -ENODEV; - } - } - - prcm_setup_regs(); - - /* Hack to prevent MPU retention when STI console is enabled. */ - { - const struct omap_sti_console_config *sti; - - sti = omap_get_config(OMAP_TAG_STI_CONSOLE, - struct omap_sti_console_config); - if (sti != NULL && sti->enable) - sti_console_enabled = 1; - } - - /* - * We copy the assembler sleep/wakeup routines to SRAM. - * These routines need to be in SRAM as that's the only - * memory the MPU can see when it wakes up. - */ - if (cpu_is_omap24xx()) { - omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend, - omap24xx_idle_loop_suspend_sz); - - omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, - omap24xx_cpu_suspend_sz); - } - - suspend_set_ops(&omap_pm_ops); - pm_idle = omap2_pm_idle; - - return 0; -} diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c deleted file mode 100644 index 43aac5f6031..00000000000 --- a/arch/arm/mach-omap2/pm34xx.c +++ /dev/null @@ -1,734 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/pm34xx.c - * - * OMAP3 Power Management Routines - * - * Copyright (C) 2006-2008 Nokia Corporation - * Tony Lindgren - * Jouni Hogander - * - * Copyright (C) 2005 Texas Instruments, Inc. - * Richard Woodruff - * - * Based on pm.c for omap1 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "cm.h" -#include "cm-regbits-34xx.h" -#include "prm-regbits-34xx.h" - -#include "prm.h" -#include "pm.h" -#include "smartreflex.h" - -struct power_state { - struct powerdomain *pwrdm; - u32 next_state; - u32 saved_state; - struct list_head node; -}; - -static LIST_HEAD(pwrst_list); - -static void (*_omap_sram_idle)(u32 *addr, int save_state); - -static void (*saved_idle)(void); - -static struct powerdomain *mpu_pwrdm; - -/* PRCM Interrupt Handler for wakeups */ -static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) -{ - u32 wkst, irqstatus_mpu; - u32 fclk, iclk; - - /* WKUP */ - wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST); - if (wkst) { - iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); - fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); - cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN); - cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN); - prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST); - while (prm_read_mod_reg(WKUP_MOD, PM_WKST)); - cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN); - cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN); - } - - /* CORE */ - wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1); - if (wkst) { - iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); - fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1); - cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1); - prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1); - while (prm_read_mod_reg(CORE_MOD, PM_WKST1)); - cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1); - cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1); - } - wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3); - if (wkst) { - iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); - fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); - cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3); - cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3); - prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3); - while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3)); - cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3); - cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3); - } - - /* PER */ - wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST); - if (wkst) { - iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); - fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); - cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN); - cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN); - prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST); - while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST)); - cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN); - cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN); - } - - if (omap_rev() > OMAP3430_REV_ES1_0) { - /* USBHOST */ - wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST); - if (wkst) { - iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, - CM_ICLKEN); - fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, - CM_FCLKEN); - cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD, - CM_ICLKEN); - cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD, - CM_FCLKEN); - prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD, - PM_WKST); - while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, - PM_WKST)); - cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD, - CM_ICLKEN); - cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD, - CM_FCLKEN); - } - } - - irqstatus_mpu = prm_read_mod_reg(OCP_MOD, - OMAP2_PRM_IRQSTATUS_MPU_OFFSET); - prm_write_mod_reg(irqstatus_mpu, OCP_MOD, - OMAP2_PRM_IRQSTATUS_MPU_OFFSET); - - while (prm_read_mod_reg(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET)); - - return IRQ_HANDLED; -} - -static void omap_sram_idle(void) -{ - /* Variable to tell what needs to be saved and restored - * in omap_sram_idle*/ - /* save_state = 0 => Nothing to save and restored */ - /* save_state = 1 => Only L1 and logic lost */ - /* save_state = 2 => Only L2 lost */ - /* save_state = 3 => L1, L2 and logic lost */ - int save_state = 0, mpu_next_state; - - if (!_omap_sram_idle) - return; - - mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); - switch (mpu_next_state) { - case PWRDM_POWER_RET: - /* No need to save context */ - save_state = 0; - break; - default: - /* Invalid state */ - printk(KERN_ERR "Invalid mpu state in sram_idle\n"); - return; - } - /* Disable smartreflex before entering WFI */ - disable_smartreflex(SR1); - disable_smartreflex(SR2); - - omap2_gpio_prepare_for_retention(); - omap_uart_prepare_idle(0); - omap_uart_prepare_idle(1); - omap_uart_prepare_idle(2); - - _omap_sram_idle(NULL, save_state); - - omap_uart_resume_idle(2); - omap_uart_resume_idle(1); - omap_uart_resume_idle(0); - omap2_gpio_resume_after_retention(); - - /* Enable smartreflex after WFI */ - enable_smartreflex(SR1); - enable_smartreflex(SR2); -} - -/* - * Check if functional clocks are enabled before entering - * sleep. This function could be behind CONFIG_PM_DEBUG - * when all drivers are configuring their sysconfig registers - * properly and using their clocks properly. - */ -static int omap3_fclks_active(void) -{ - u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0, - fck_cam = 0, fck_per = 0, fck_usbhost = 0; - - fck_core1 = cm_read_mod_reg(CORE_MOD, - CM_FCLKEN1); - if (omap_rev() > OMAP3430_REV_ES1_0) { - fck_core3 = cm_read_mod_reg(CORE_MOD, - OMAP3430ES2_CM_FCLKEN3); - fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, - CM_FCLKEN); - fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, - CM_FCLKEN); - } else - fck_sgx = cm_read_mod_reg(GFX_MOD, - OMAP3430ES2_CM_FCLKEN3); - fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD, - CM_FCLKEN); - fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD, - CM_FCLKEN); - fck_per = cm_read_mod_reg(OMAP3430_PER_MOD, - CM_FCLKEN); - - /* Ignore UART clocks. These are handled by UART core (serial.c) */ - fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2); - fck_per &= ~OMAP3430_EN_UART3; - - if (fck_core1 | fck_core3 | fck_sgx | fck_dss | - fck_cam | fck_per | fck_usbhost) - return 1; - return 0; -} - -static int omap3_can_sleep(void) -{ - if (!enable_dyn_sleep) - return 0; - if (!omap_uart_can_sleep()) - return 0; - if (omap3_fclks_active()) - return 0; - if (atomic_read(&sleep_block) > 0) - return 0; - return 1; -} - -/* This sets pwrdm state (other than mpu & core. Currently only ON & - * RET are supported. Function is assuming that clkdm doesn't have - * hw_sup mode enabled. */ -static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) -{ - u32 cur_state; - int sleep_switch = 0; - int ret = 0; - - if (pwrdm == NULL || IS_ERR(pwrdm)) - return -EINVAL; - - while (!(pwrdm->pwrsts & (1 << state))) { - if (state == PWRDM_POWER_OFF) - return ret; - state--; - } - - cur_state = pwrdm_read_next_pwrst(pwrdm); - if (cur_state == state) - return ret; - - if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { - omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); - sleep_switch = 1; - pwrdm_wait_transition(pwrdm); - } - - ret = pwrdm_set_next_pwrst(pwrdm, state); - if (ret) { - printk(KERN_ERR "Unable to set state of powerdomain: %s\n", - pwrdm->name); - goto err; - } - - if (sleep_switch) { - omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); - pwrdm_wait_transition(pwrdm); - } - -err: - return ret; -} - -static void omap3_pm_idle(void) -{ - local_irq_disable(); - local_fiq_disable(); - - if (!omap3_can_sleep()) - goto out; - - if (omap_irq_pending()) - goto out; - - omap_sram_idle(); - -out: - local_fiq_enable(); - local_irq_enable(); -} - -static int omap3_pm_prepare(void) -{ - saved_idle = pm_idle; - pm_idle = NULL; - return 0; -} - -static int omap3_pm_suspend(void) -{ - struct power_state *pwrst; - int state, ret = 0; - - /* Read current next_pwrsts */ - list_for_each_entry(pwrst, &pwrst_list, node) - pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); - /* Set ones wanted by suspend */ - list_for_each_entry(pwrst, &pwrst_list, node) { - if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) - goto restore; - if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) - goto restore; - } - - omap_uart_prepare_suspend(); - omap_sram_idle(); - -restore: - /* Restore next_pwrsts */ - list_for_each_entry(pwrst, &pwrst_list, node) { - set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); - state = pwrdm_read_prev_pwrst(pwrst->pwrdm); - if (state > pwrst->next_state) { - printk(KERN_INFO "Powerdomain (%s) didn't enter " - "target state %d\n", - pwrst->pwrdm->name, pwrst->next_state); - ret = -1; - } - } - if (ret) - printk(KERN_ERR "Could not enter target state in pm_suspend\n"); - else - printk(KERN_INFO "Successfully put all powerdomains " - "to target state\n"); - - return ret; -} - -static int omap3_pm_enter(suspend_state_t state) -{ - int ret = 0; - - switch (state) { - case PM_SUSPEND_STANDBY: - case PM_SUSPEND_MEM: - ret = omap3_pm_suspend(); - break; - default: - ret = -EINVAL; - } - - return ret; -} - -static void omap3_pm_finish(void) -{ - pm_idle = saved_idle; -} - -static struct platform_suspend_ops omap_pm_ops = { - .prepare = omap3_pm_prepare, - .enter = omap3_pm_enter, - .finish = omap3_pm_finish, - .valid = suspend_valid_only_mem, -}; - - -/** - * omap3_iva_idle(): ensure IVA is in idle so it can be put into - * retention - * - * In cases where IVA2 is activated by bootcode, it may prevent - * full-chip retention or off-mode because it is not idle. This - * function forces the IVA2 into idle state so it can go - * into retention/off and thus allow full-chip retention/off. - * - **/ -static void __init omap3_iva_idle(void) -{ - /* ensure IVA2 clock is disabled */ - cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); - - /* Reset IVA2 */ - prm_write_mod_reg(OMAP3430_RST1_IVA2 | - OMAP3430_RST2_IVA2 | - OMAP3430_RST3_IVA2, - OMAP3430_IVA2_MOD, RM_RSTCTRL); - - /* Enable IVA2 clock */ - cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, - OMAP3430_IVA2_MOD, CM_FCLKEN); - - /* Set IVA2 boot mode to 'idle' */ - omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, - OMAP343X_CONTROL_IVA2_BOOTMOD); - - /* Un-reset IVA2 */ - prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); - - /* Disable IVA2 clock */ - cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); - - /* Reset IVA2 */ - prm_write_mod_reg(OMAP3430_RST1_IVA2 | - OMAP3430_RST2_IVA2 | - OMAP3430_RST3_IVA2, - OMAP3430_IVA2_MOD, RM_RSTCTRL); -} - -static void __init prcm_setup_regs(void) -{ - /* reset modem */ - prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | - OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, - CORE_MOD, RM_RSTCTRL); - prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); - - /* XXX Reset all wkdeps. This should be done when initializing - * powerdomains */ - prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); - prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); - if (omap_rev() > OMAP3430_REV_ES1_0) { - prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); - } else - prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); - - /* - * Enable interface clock autoidle for all modules. - * Note that in the long run this should be done by clockfw - */ - cm_write_mod_reg( - OMAP3430ES2_AUTO_MMC3 | - OMAP3430ES2_AUTO_ICR | - OMAP3430_AUTO_AES2 | - OMAP3430_AUTO_SHA12 | - OMAP3430_AUTO_DES2 | - OMAP3430_AUTO_MMC2 | - OMAP3430_AUTO_MMC1 | - OMAP3430_AUTO_MSPRO | - OMAP3430_AUTO_HDQ | - OMAP3430_AUTO_MCSPI4 | - OMAP3430_AUTO_MCSPI3 | - OMAP3430_AUTO_MCSPI2 | - OMAP3430_AUTO_MCSPI1 | - OMAP3430_AUTO_I2C3 | - OMAP3430_AUTO_I2C2 | - OMAP3430_AUTO_I2C1 | - OMAP3430_AUTO_UART2 | - OMAP3430_AUTO_UART1 | - OMAP3430_AUTO_GPT11 | - OMAP3430_AUTO_GPT10 | - OMAP3430_AUTO_MCBSP5 | - OMAP3430_AUTO_MCBSP1 | - OMAP3430ES1_AUTO_FAC | /* This is es1 only */ - OMAP3430_AUTO_MAILBOXES | - OMAP3430_AUTO_OMAPCTRL | - OMAP3430ES1_AUTO_FSHOSTUSB | - OMAP3430_AUTO_HSOTGUSB | - OMAP3430ES1_AUTO_D2D | /* This is es1 only */ - OMAP3430_AUTO_SSI, - CORE_MOD, CM_AUTOIDLE1); - - cm_write_mod_reg( - OMAP3430_AUTO_PKA | - OMAP3430_AUTO_AES1 | - OMAP3430_AUTO_RNG | - OMAP3430_AUTO_SHA11 | - OMAP3430_AUTO_DES1, - CORE_MOD, CM_AUTOIDLE2); - - if (omap_rev() > OMAP3430_REV_ES1_0) { - cm_write_mod_reg( - OMAP3430ES2_AUTO_USBTLL, - CORE_MOD, CM_AUTOIDLE3); - } - - cm_write_mod_reg( - OMAP3430_AUTO_WDT2 | - OMAP3430_AUTO_WDT1 | - OMAP3430_AUTO_GPIO1 | - OMAP3430_AUTO_32KSYNC | - OMAP3430_AUTO_GPT12 | - OMAP3430_AUTO_GPT1 , - WKUP_MOD, CM_AUTOIDLE); - - cm_write_mod_reg( - OMAP3430_AUTO_DSS, - OMAP3430_DSS_MOD, - CM_AUTOIDLE); - - cm_write_mod_reg( - OMAP3430_AUTO_CAM, - OMAP3430_CAM_MOD, - CM_AUTOIDLE); - - cm_write_mod_reg( - OMAP3430_AUTO_GPIO6 | - OMAP3430_AUTO_GPIO5 | - OMAP3430_AUTO_GPIO4 | - OMAP3430_AUTO_GPIO3 | - OMAP3430_AUTO_GPIO2 | - OMAP3430_AUTO_WDT3 | - OMAP3430_AUTO_UART3 | - OMAP3430_AUTO_GPT9 | - OMAP3430_AUTO_GPT8 | - OMAP3430_AUTO_GPT7 | - OMAP3430_AUTO_GPT6 | - OMAP3430_AUTO_GPT5 | - OMAP3430_AUTO_GPT4 | - OMAP3430_AUTO_GPT3 | - OMAP3430_AUTO_GPT2 | - OMAP3430_AUTO_MCBSP4 | - OMAP3430_AUTO_MCBSP3 | - OMAP3430_AUTO_MCBSP2, - OMAP3430_PER_MOD, - CM_AUTOIDLE); - - if (omap_rev() > OMAP3430_REV_ES1_0) { - cm_write_mod_reg( - OMAP3430ES2_AUTO_USBHOST, - OMAP3430ES2_USBHOST_MOD, - CM_AUTOIDLE); - } - - /* - * Set all plls to autoidle. This is needed until autoidle is - * enabled by clockfw - */ - cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, - OMAP3430_IVA2_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, - MPU_MOD, - CM_AUTOIDLE2); - cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | - (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), - PLL_MOD, - CM_AUTOIDLE); - cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, - PLL_MOD, - CM_AUTOIDLE2); - - /* - * Enable control of expternal oscillator through - * sys_clkreq. In the long run clock framework should - * take care of this. - */ - prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, - 1 << OMAP_AUTOEXTCLKMODE_SHIFT, - OMAP3430_GR_MOD, - OMAP3_PRM_CLKSRC_CTRL_OFFSET); - - /* setup wakup source */ - prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | - OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, - WKUP_MOD, PM_WKEN); - /* No need to write EN_IO, that is always enabled */ - prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | - OMAP3430_EN_GPT12, - WKUP_MOD, OMAP3430_PM_MPUGRPSEL); - /* For some reason IO doesn't generate wakeup event even if - * it is selected to mpu wakeup goup */ - prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, - OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET); - - omap3_iva_idle(); -} - -static int __init pwrdms_setup(struct powerdomain *pwrdm) -{ - struct power_state *pwrst; - - if (!pwrdm->pwrsts) - return 0; - - pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL); - if (!pwrst) - return -ENOMEM; - pwrst->pwrdm = pwrdm; - pwrst->next_state = PWRDM_POWER_RET; - list_add(&pwrst->node, &pwrst_list); - - if (pwrdm_has_hdwr_sar(pwrdm)) - pwrdm_enable_hdwr_sar(pwrdm); - - return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); -} - -/* - * Enable hw supervised mode for all clockdomains if it's - * supported. Initiate sleep transition for other clockdomains, if - * they are not used - */ -static int __init clkdms_setup(struct clockdomain *clkdm) -{ - if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) - omap2_clkdm_allow_idle(clkdm); - else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && - atomic_read(&clkdm->usecount) == 0) - omap2_clkdm_sleep(clkdm); - return 0; -} - -int __init omap3_pm_init(void) -{ - struct power_state *pwrst, *tmp; - int ret; - - printk(KERN_ERR "Power Management for TI OMAP3.\n"); - - /* XXX prcm_setup_regs needs to be before enabling hw - * supervised mode for powerdomains */ - prcm_setup_regs(); - - ret = request_irq(INT_34XX_PRCM_MPU_IRQ, - (irq_handler_t)prcm_interrupt_handler, - IRQF_DISABLED, "prcm", NULL); - if (ret) { - printk(KERN_ERR "request_irq failed to register for 0x%x\n", - INT_34XX_PRCM_MPU_IRQ); - goto err1; - } - - ret = pwrdm_for_each(pwrdms_setup); - if (ret) { - printk(KERN_ERR "Failed to setup powerdomains\n"); - goto err2; - } - - (void) clkdm_for_each(clkdms_setup); - - mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); - if (mpu_pwrdm == NULL) { - printk(KERN_ERR "Failed to get mpu_pwrdm\n"); - goto err2; - } - - _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, - omap34xx_cpu_suspend_sz); - - suspend_set_ops(&omap_pm_ops); - - pm_idle = omap3_pm_idle; - -err1: - return ret; -err2: - free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); - list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { - list_del(&pwrst->node); - kfree(pwrst); - } - return ret; -} - -static void __init configure_vc(void) -{ - prm_write_mod_reg((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) | - (R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT), - OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET); - prm_write_mod_reg((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) | - (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT), - OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET); - - prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON << - OMAP3430_VC_CMD_ON_SHIFT) | - (OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) | - (OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) | - (OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT), - OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET); - - prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON << - OMAP3430_VC_CMD_ON_SHIFT) | - (OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) | - (OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) | - (OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT), - OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET); - - prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1, - OMAP3430_GR_MOD, - OMAP3_PRM_VC_CH_CONF_OFFSET); - - prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN, - OMAP3430_GR_MOD, - OMAP3_PRM_VC_I2C_CFG_OFFSET); - - /* Setup voltctrl and other setup times */ - prm_write_mod_reg(OMAP3430_AUTO_RET, OMAP3430_GR_MOD, - OMAP3_PRM_VOLTCTRL_OFFSET); - - prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD, - OMAP3_PRM_CLKSETUP_OFFSET); - prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 << - OMAP3430_SETUP_TIME2_SHIFT) | - (OMAP3430_VOLTSETUP_TIME1 << - OMAP3430_SETUP_TIME1_SHIFT), - OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET); - - prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD, - OMAP3_PRM_VOLTOFFSET_OFFSET); - prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD, - OMAP3_PRM_VOLTSETUP2_OFFSET); -} - -static int __init omap3_pm_early_init(void) -{ - prm_clear_mod_reg_bits(OMAP3430_OFFMODE_POL, OMAP3430_GR_MOD, - OMAP3_PRM_POLCTRL_OFFSET); - - configure_vc(); - - return 0; -} - -arch_initcall(omap3_pm_early_init); diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index cb1ae84e092..812d50ee495 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -276,8 +276,6 @@ /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ #define OMAP3430_EN_GPIO1 (1 << 3) #define OMAP3430_EN_GPIO1_SHIFT 3 -#define OMAP3430_EN_GPT12 (1 << 1) -#define OMAP3430_EN_GPT12_SHIFT 1 #define OMAP3430_EN_GPT1 (1 << 0) #define OMAP3430_EN_GPT1_SHIFT 0 diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 12c0e03a0df..f945156d558 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -19,7 +19,6 @@ #include #include -#include #include #include "clock.h" @@ -44,18 +43,9 @@ void omap_prcm_arch_reset(char mode) if (cpu_is_omap24xx()) prcm_offs = WKUP_MOD; - else if (cpu_is_omap34xx()) { - u32 l; - + else if (cpu_is_omap34xx()) prcm_offs = OMAP3430_GR_MOD; - l = ('B' << 24) | ('M' << 16) | mode; - /* Reserve the first word in scratchpad for communicating - * with the boot ROM. A pointer to a data structure - * describing the boot process can be stored there, - * cf. OMAP34xx TRM, Initialization / Software Booting - * Configuration. */ - omap_writel(l, OMAP343X_SCRATCHPAD + 4); - } else + else WARN_ON(1); prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index d73eee8d3ac..c6a7940f428 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -435,10 +435,10 @@ /* PM_PWSTST_EMU specific bits */ /* PRM_VC_SMPS_SA */ -#define OMAP3430_SMPS_SA1_SHIFT 16 -#define OMAP3430_SMPS_SA1_MASK (0x7f << 16) -#define OMAP3430_SMPS_SA0_SHIFT 0 -#define OMAP3430_SMPS_SA0_MASK (0x7f << 0) +#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 +#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) +#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 +#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) /* PRM_VC_SMPS_VOL_RA */ #define OMAP3430_VOLRA1_SHIFT 16 @@ -452,7 +452,7 @@ #define OMAP3430_CMDRA0_SHIFT 0 #define OMAP3430_CMDRA0_MASK (0xff << 0) -/* PRM_VC_CMD_VAL */ +/* PRM_VC_CMD_VAL_0 specific bits */ #define OMAP3430_VC_CMD_ON_SHIFT 24 #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) #define OMAP3430_VC_CMD_ONLP_SHIFT 16 @@ -462,17 +462,7 @@ #define OMAP3430_VC_CMD_OFF_SHIFT 0 #define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0) -/* PRM_VC_CMD_VAL_0 specific bits */ -#define OMAP3430_VC_CMD_VAL0_ON (0x3 << 4) -#define OMAP3430_VC_CMD_VAL0_ONLP (0x3 << 3) -#define OMAP3430_VC_CMD_VAL0_RET (0x3 << 3) -#define OMAP3430_VC_CMD_VAL0_OFF (0x3 << 4) - /* PRM_VC_CMD_VAL_1 specific bits */ -#define OMAP3430_VC_CMD_VAL1_ON (0xB << 2) -#define OMAP3430_VC_CMD_VAL1_ONLP (0x3 << 3) -#define OMAP3430_VC_CMD_VAL1_RET (0x3 << 3) -#define OMAP3430_VC_CMD_VAL1_OFF (0xB << 2) /* PRM_VC_CH_CONF */ #define OMAP3430_CMD1 (1 << 20) @@ -531,13 +521,6 @@ #define OMAP3430_AUTO_RET (1 << 1) #define OMAP3430_AUTO_SLEEP (1 << 0) -/* Constants to define setup durations */ -#define OMAP3430_CLKSETUP_DURATION 0xff -#define OMAP3430_VOLTSETUP_TIME2 0xfff -#define OMAP3430_VOLTSETUP_TIME1 0xfff -#define OMAP3430_VOLTOFFSET_DURATION 0xff -#define OMAP3430_VOLTSETUP2_DURATION 0xff - /* PRM_SRAM_PCHARGE */ #define OMAP3430_PCHARGE_TIME_SHIFT 0 #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0) diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 3c6418e8e71..826d326b806 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -4,8 +4,8 @@ /* * OMAP2/3 Power/Reset Management (PRM) register definitions * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2008 Nokia Corporation + * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007 Nokia Corporation * * Written by Paul Walmsley * @@ -16,16 +16,21 @@ #include "prcm-common.h" +#ifndef __ASSEMBLER__ +#define OMAP_PRM_REGADDR(module, reg) \ + IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg)) +#else #define OMAP2420_PRM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) #define OMAP2430_PRM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) #define OMAP34XX_PRM_REGADDR(module, reg) \ IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) +#endif /* * Architecture-specific global PRM registers - * Use prm_{read,write}_mod_reg() with these registers. + * Use __raw_{read,write}l() with these registers. * * With a few exceptions, these are the register names beginning with * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the @@ -33,66 +38,80 @@ * */ -/* Common registers for 24xx and 34xx in OCP_MOD */ -#define OMAP2_PRM_IRQSTATUS_MPU_OFFSET 0x0018 -#define OMAP2_PRM_IRQENABLE_MPU_OFFSET 0x001c - -/* 24xx register offsets in OCP_MOD */ -#define OMAP24XX_PRM_REVISION_OFFSET 0x0000 -#define OMAP24XX_PRM_SYSCONFIG_OFFSET 0x0010 - -/* 34xx register offsets in OCP_MOD */ -#define OMAP3430_PRM_REVISION_OFFSET 0x0004 -#define OMAP3430_PRM_SYSCONFIG_OFFSET 0x0014 - -/* 24xx register offsets in OMAP24XX_GR_MOD (Same as OCP_MOD for 24xx) */ +/* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */ #define OMAP24XX_PRCM_VOLTCTRL_OFFSET 0x0050 -#define OMAP24XX_PRCM_VOLTST_OFFSET 0x0054 -#define OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET 0x0060 -#define OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 #define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET 0x0080 -#define OMAP24XX_PRCM_CLKCFG_STATUS_OFFSET 0x0084 -#define OMAP24XX_PRCM_VOLTSETUP_OFFSET 0x0090 -#define OMAP24XX_PRCM_CLKSSETUP_OFFSET 0x0094 -#define OMAP24XX_PRCM_POLCTRL_OFFSET 0x0098 - -/* 34xx register offsets in GR_MOD */ -#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 -#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 -#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 -#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c -#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 -#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 -#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 -#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c -#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 -#define OMAP3_PRM_RSTTIME_OFFSET 0x0054 -#define OMAP3_PRM_RSTST_OFFSET 0x0058 -#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 -#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 -#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 -#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 -#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 -#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 -#define OMAP3_PRM_POLCTRL_OFFSET 0x009c -#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 -#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 -#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 -#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 -#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc -#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 -#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 -#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 -#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 -#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 -#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc -#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 -#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 - -/* 34xx register offsets in CCR_MOD */ -#define OMAP3_PRM_CLKSEL_OFFSET 0x0040 -#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 + +/* 242x GR_MOD registers, use these only for assembly code */ +#define OMAP242X_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_VOLTCTRL_OFFSET) +#define OMAP242X_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) + +/* 243x GR_MOD registers, use these only for assembly code */ +#define OMAP243X_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_VOLTCTRL_OFFSET) +#define OMAP243X_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) + +/* These will disappear */ +#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000) +#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010) + +#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) + +#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054) +#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060) +#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070) +#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078) +#define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080) +#define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084) +#define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090) +#define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094) +#define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098) + +#define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004) +#define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014) + +#define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) + + +#define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) +#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) +#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) +#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) +#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) +#define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) +#define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) +#define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) +#define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) +#define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) +#define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) +#define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) +#define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) +#define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) +#define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) +#define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) +#define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) +#define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) +#define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) +#define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) +#define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) +#define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) +#define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) +#define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) +#define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) +#define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) +#define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) +#define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) +#define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) +#define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) +#define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) + +#define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) +#define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) /* * Module specific PRM registers from PRM_BASE + domain offset @@ -146,6 +165,7 @@ #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc + #ifndef __ASSEMBLER__ /* Power/reset management domain register get/set */ diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index 993fd253cb9..2a30060cb4b 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c @@ -56,12 +56,9 @@ struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r) { struct omap_sdrc_params *sp; - if (!sdrc_init_params) - return NULL; - sp = sdrc_init_params; - while (sp->rate && sp->rate != r) + while (sp->rate != r) sp++; if (!sp->rate) diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 479dc8c8837..0afdad5ae9f 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c @@ -1,7 +1,7 @@ /* - * linux/arch/arm/mach-omap2/memory.c + * linux/arch/arm/mach-omap2/sdrc2xxx.c * - * Memory timing related functions for OMAP2xxx + * SDRAM timing related functions for OMAP2xxx * * Copyright (C) 2005, 2008 Texas Instruments Inc. * Copyright (C) 2005, 2008 Nokia Corporation @@ -28,10 +28,8 @@ #include #include -#include "clock.h" - #include "prm.h" - +#include "clock.h" #include #include "sdrc.h" @@ -101,8 +99,7 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) m_type = omap2xxx_sdrc_get_type(); local_irq_save(flags); - prm_write_mod_reg(0xffff, OMAP24XX_GR_MOD, - OMAP24XX_PRCM_VOLTSETUP_OFFSET); + __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); curr_perf_level = level; local_irq_restore(flags); diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index fd5b9f83e0b..4dcf39c285b 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -6,8 +6,6 @@ * Copyright (C) 2005-2008 Nokia Corporation * Author: Paul Mundt * - * Major rework for PM support by Kevin Hilman - * * Based off of arch/arm/mach-omap/omap1/serial.c * * This file is subject to the terms and conditions of the GNU General Public @@ -23,48 +21,9 @@ #include #include -#include -#include - -#include "prm.h" -#include "pm.h" -#include "prm-regbits-34xx.h" - -#define DEFAULT_TIMEOUT (5 * HZ) - -struct omap_uart_state { - int num; - int can_sleep; - struct timer_list timer; - u32 timeout; - - void __iomem *wk_st; - void __iomem *wk_en; - u32 wk_mask; - u32 padconf; - struct clk *ick; - struct clk *fck; - int clocked; - - struct plat_serial8250_port *p; - struct list_head node; - -#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) - int context_valid; - - /* Registers to be saved/restored for OFF-mode */ - u16 dll; - u16 dlh; - u16 ier; - u16 sysc; - u16 scr; - u16 wer; -#endif -}; - -static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS]; -static LIST_HEAD(uart_list); +static struct clk *uart_ick[OMAP_MAX_NR_PORTS]; +static struct clk *uart_fck[OMAP_MAX_NR_PORTS]; static struct plat_serial8250_port serial_platform_data[] = { { @@ -115,356 +74,30 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, * properly. Note that the TX watermark initialization may not be needed * once the 8250.c watermark handling code is merged. */ -static inline void __init omap_uart_reset(struct omap_uart_state *uart) +static inline void __init omap_serial_reset(struct plat_serial8250_port *p) { - struct plat_serial8250_port *p = uart->p; - serial_write_reg(p, UART_OMAP_MDR1, 0x07); serial_write_reg(p, UART_OMAP_SCR, 0x08); serial_write_reg(p, UART_OMAP_MDR1, 0x00); serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); } -static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) -{ - if (uart->clocked) - return; - - clk_enable(uart->ick); - clk_enable(uart->fck); - uart->clocked = 1; -} - -#ifdef CONFIG_PM -#ifdef CONFIG_ARCH_OMAP3 - -static int enable_off_mode; /* to be removed by full off-mode patches */ - -static void omap_uart_save_context(struct omap_uart_state *uart) -{ - u16 lcr = 0; - struct plat_serial8250_port *p = uart->p; - - if (!enable_off_mode) - return; - - lcr = serial_read_reg(p, UART_LCR); - serial_write_reg(p, UART_LCR, 0xBF); - uart->dll = serial_read_reg(p, UART_DLL); - uart->dlh = serial_read_reg(p, UART_DLM); - serial_write_reg(p, UART_LCR, lcr); - uart->ier = serial_read_reg(p, UART_IER); - uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); - uart->scr = serial_read_reg(p, UART_OMAP_SCR); - uart->wer = serial_read_reg(p, UART_OMAP_WER); - - uart->context_valid = 1; -} - -static void omap_uart_restore_context(struct omap_uart_state *uart) -{ - u16 efr = 0; - struct plat_serial8250_port *p = uart->p; - - if (!enable_off_mode) - return; - - if (!uart->context_valid) - return; - - uart->context_valid = 0; - - serial_write_reg(p, UART_OMAP_MDR1, 0x7); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - efr = serial_read_reg(p, UART_EFR); - serial_write_reg(p, UART_EFR, UART_EFR_ECB); - serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(p, UART_IER, 0x0); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - serial_write_reg(p, UART_DLL, uart->dll); - serial_write_reg(p, UART_DLM, uart->dlh); - serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(p, UART_IER, uart->ier); - serial_write_reg(p, UART_FCR, 0xA1); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - serial_write_reg(p, UART_EFR, efr); - serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); - serial_write_reg(p, UART_OMAP_SCR, uart->scr); - serial_write_reg(p, UART_OMAP_WER, uart->wer); - serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); - serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ -} -#else -static inline void omap_uart_save_context(struct omap_uart_state *uart) {} -static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} -#endif /* CONFIG_ARCH_OMAP3 */ - -static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, - int enable) +void omap_serial_enable_clocks(int enable) { - struct plat_serial8250_port *p = uart->p; - u16 sysc; - - sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7; - if (enable) - sysc |= 0x2 << 3; - else - sysc |= 0x1 << 3; - - serial_write_reg(p, UART_OMAP_SYSC, sysc); -} - -static inline void omap_uart_restore(struct omap_uart_state *uart) -{ - omap_uart_enable_clocks(uart); - omap_uart_restore_context(uart); -} - -static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) -{ - if (!uart->clocked) - return; - - omap_uart_save_context(uart); - uart->clocked = 0; - clk_disable(uart->ick); - clk_disable(uart->fck); -} - -static void omap_uart_block_sleep(struct omap_uart_state *uart) -{ - omap_uart_restore(uart); - - omap_uart_smart_idle_enable(uart, 0); - uart->can_sleep = 0; - mod_timer(&uart->timer, jiffies + uart->timeout); -} - -static void omap_uart_allow_sleep(struct omap_uart_state *uart) -{ - if (!uart->clocked) - return; - - omap_uart_smart_idle_enable(uart, 1); - uart->can_sleep = 1; - del_timer(&uart->timer); -} - -static void omap_uart_idle_timer(unsigned long data) -{ - struct omap_uart_state *uart = (struct omap_uart_state *)data; - - omap_uart_allow_sleep(uart); -} - -void omap_uart_prepare_idle(int num) -{ - struct omap_uart_state *uart; - - list_for_each_entry(uart, &uart_list, node) { - if (!clocks_off_while_idle) - continue; - - if (num == uart->num && uart->can_sleep) { - omap_uart_disable_clocks(uart); - return; - } - } -} - -void omap_uart_resume_idle(int num) -{ - struct omap_uart_state *uart; - - list_for_each_entry(uart, &uart_list, node) { - if (num == uart->num) { - omap_uart_restore(uart); - - /* Check for IO pad wakeup */ - if (cpu_is_omap34xx() && uart->padconf) { - u16 p = omap_ctrl_readw(uart->padconf); - - if (p & OMAP3_PADCONF_WAKEUPEVENT0) - omap_uart_block_sleep(uart); + int i; + for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { + if (uart_ick[i] && uart_fck[i]) { + if (enable) { + clk_enable(uart_ick[i]); + clk_enable(uart_fck[i]); + } else { + clk_disable(uart_ick[i]); + clk_disable(uart_fck[i]); } - - /* Check for normal UART wakeup */ - if (__raw_readl(uart->wk_st) & uart->wk_mask) - omap_uart_block_sleep(uart); - - return; - } - } -} - -void omap_uart_prepare_suspend(void) -{ - struct omap_uart_state *uart; - - list_for_each_entry(uart, &uart_list, node) { - omap_uart_allow_sleep(uart); - } -} - -int omap_uart_can_sleep(void) -{ - struct omap_uart_state *uart; - int can_sleep = 1; - - list_for_each_entry(uart, &uart_list, node) { - if (!uart->clocked) - continue; - - if (!uart->can_sleep) { - can_sleep = 0; - continue; - } - - /* This UART can now safely sleep. */ - omap_uart_allow_sleep(uart); - } - - return can_sleep; -} - -/** - * omap_uart_interrupt() - * - * This handler is used only to detect that *any* UART interrupt has - * occurred. It does _nothing_ to handle the interrupt. Rather, - * any UART interrupt will trigger the inactivity timer so the - * UART will not idle or sleep for its timeout period. - * - **/ -static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) -{ - struct omap_uart_state *uart = dev_id; - - omap_uart_block_sleep(uart); - - return IRQ_NONE; -} - -static u32 sleep_timeout = DEFAULT_TIMEOUT; - -static void omap_uart_idle_init(struct omap_uart_state *uart) -{ - u32 v; - struct plat_serial8250_port *p = uart->p; - int ret; - - uart->can_sleep = 0; - uart->timeout = sleep_timeout; - setup_timer(&uart->timer, omap_uart_idle_timer, - (unsigned long) uart); - mod_timer(&uart->timer, jiffies + uart->timeout); - omap_uart_smart_idle_enable(uart, 0); - - if (cpu_is_omap34xx()) { - u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD; - u32 wk_mask = 0; - u32 padconf = 0; - - uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); - uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); - switch (uart->num) { - case 0: - wk_mask = OMAP3430_ST_UART1_MASK; - padconf = 0x182; - break; - case 1: - wk_mask = OMAP3430_ST_UART2_MASK; - padconf = 0x17a; - break; - case 2: - wk_mask = OMAP3430_ST_UART3_MASK; - padconf = 0x19e; - break; - } - uart->wk_mask = wk_mask; - uart->padconf = padconf; - } else if (cpu_is_omap24xx()) { - u32 wk_mask = 0; - - if (cpu_is_omap2430()) { - uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1); - uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1); - } else if (cpu_is_omap2420()) { - uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1); - uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1); } - switch (uart->num) { - case 0: - wk_mask = OMAP24XX_ST_UART1_MASK; - break; - case 1: - wk_mask = OMAP24XX_ST_UART2_MASK; - break; - case 2: - wk_mask = OMAP24XX_ST_UART3_MASK; - break; - } - uart->wk_mask = wk_mask; - } else { - uart->wk_en = 0; - uart->wk_st = 0; - uart->wk_mask = 0; - uart->padconf = 0; - } - - /* Set wake-enable bit */ - if (uart->wk_en && uart->wk_mask) { - v = __raw_readl(uart->wk_en); - v |= uart->wk_mask; - __raw_writel(v, uart->wk_en); - } - - /* Ensure IOPAD wake-enables are set */ - if (cpu_is_omap34xx() && uart->padconf) { - u16 v; - - v = omap_ctrl_readw(uart->padconf); - v |= OMAP3_PADCONF_WAKEUPENABLE0; - omap_ctrl_writew(v, uart->padconf); } - - p->flags |= UPF_SHARE_IRQ; - ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, - "serial idle", (void *)uart); - WARN_ON(ret); } -static ssize_t sleep_timeout_show(struct kobject *kobj, - struct kobj_attribute *attr, - char *buf) -{ - return sprintf(buf, "%u\n", sleep_timeout / HZ); -} - -static ssize_t sleep_timeout_store(struct kobject *kobj, - struct kobj_attribute *attr, - const char *buf, size_t n) -{ - struct omap_uart_state *uart; - unsigned int value; - - if (sscanf(buf, "%u", &value) != 1) { - printk(KERN_ERR "sleep_timeout_store: Invalid value\n"); - return -EINVAL; - } - sleep_timeout = value * HZ; - list_for_each_entry(uart, &uart_list, node) - uart->timeout = sleep_timeout; - return n; -} - -static struct kobj_attribute sleep_timeout_attr = - __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); - -#else -static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} -#endif /* CONFIG_PM */ - void __init omap_serial_init(void) { int i; @@ -484,7 +117,6 @@ void __init omap_serial_init(void) for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { struct plat_serial8250_port *p = serial_platform_data + i; - struct omap_uart_state *uart = &omap_uart[i]; if (!(info->enabled_uarts & (1 << i))) { p->membase = NULL; @@ -493,30 +125,22 @@ void __init omap_serial_init(void) } sprintf(name, "uart%d_ick", i+1); - uart->ick = clk_get(NULL, name); - if (IS_ERR(uart->ick)) { + uart_ick[i] = clk_get(NULL, name); + if (IS_ERR(uart_ick[i])) { printk(KERN_ERR "Could not get uart%d_ick\n", i+1); - uart->ick = NULL; - } + uart_ick[i] = NULL; + } else + clk_enable(uart_ick[i]); sprintf(name, "uart%d_fck", i+1); - uart->fck = clk_get(NULL, name); - if (IS_ERR(uart->fck)) { + uart_fck[i] = clk_get(NULL, name); + if (IS_ERR(uart_fck[i])) { printk(KERN_ERR "Could not get uart%d_fck\n", i+1); - uart->fck = NULL; - } - - if (!uart->ick || !uart->fck) - continue; - - uart->num = i; - p->private_data = uart; - uart->p = p; - list_add(&uart->node, &uart_list); + uart_fck[i] = NULL; + } else + clk_enable(uart_fck[i]); - omap_uart_enable_clocks(uart); - omap_uart_reset(uart); - omap_uart_idle_init(uart); + omap_serial_reset(p); } } @@ -530,15 +154,6 @@ static struct platform_device serial_device = { static int __init omap_init(void) { - int ret; - - ret = platform_device_register(&serial_device); - -#ifdef CONFIG_PM - if (!ret) - ret = sysfs_create_file(&serial_device.dev.kobj, - &sleep_timeout_attr.attr); -#endif - return ret; + return platform_device_register(&serial_device); } arch_initcall(omap_init); diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S deleted file mode 100644 index 125b75affeb..00000000000 --- a/arch/arm/mach-omap2/sleep34xx.S +++ /dev/null @@ -1,544 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/sleep.S - * - * (C) Copyright 2007 - * Texas Instruments - * Karthik Dasu - * - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include - -#include "prm.h" -#include "sdrc.h" - -#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ - OMAP3430_PM_PREPWSTST) -#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ - OMAP3430_PM_PREPWSTST) -#define PM_PWSTCTRL_MPU_P OMAP34XX_PRM_REGADDR(MPU_MOD, PM_PWSTCTRL) -#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is - * available */ -#define SCRATCHPAD_BASE_P OMAP343X_CTRL_REGADDR(\ - OMAP343X_CONTROL_MEM_WKUP +\ - SCRATCHPAD_MEM_OFFS) -#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) - - .text -/* Function call to get the restore pointer for resume from OFF */ -ENTRY(get_restore_pointer) - stmfd sp!, {lr} @ save registers on stack - adr r0, restore - ldmfd sp!, {pc} @ restore regs and return -ENTRY(get_restore_pointer_sz) - .word . - get_restore_pointer_sz -/* - * Forces OMAP into idle state - * - * omap34xx_suspend() - This bit of code just executes the WFI - * for normal idles. - * - * Note: This code get's copied to internal SRAM at boot. When the OMAP - * wakes up it continues execution at the point it went to sleep. - */ -ENTRY(omap34xx_cpu_suspend) - stmfd sp!, {r0-r12, lr} @ save registers on stack -loop: - /*b loop*/ @Enable to debug by stepping through code - /* r0 contains restore pointer in sdram */ - /* r1 contains information about saving context */ - ldr r4, sdrc_power @ read the SDRC_POWER register - ldr r5, [r4] @ read the contents of SDRC_POWER - orr r5, r5, #0x40 @ enable self refresh on idle req - str r5, [r4] @ write back to SDRC_POWER register - - cmp r1, #0x0 - /* If context save is required, do that and execute wfi */ - bne save_context_wfi - /* Data memory barrier and Data sync barrier */ - mov r1, #0 - mcr p15, 0, r1, c7, c10, 4 - mcr p15, 0, r1, c7, c10, 5 - - wfi @ wait for interrupt - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - bl i_dll_wait - - ldmfd sp!, {r0-r12, pc} @ restore regs and return -restore: - /* b restore*/ @ Enable to debug restore code - /* Check what was the reason for mpu reset and store the reason in r9*/ - /* 1 - Only L1 and logic lost */ - /* 2 - Only L2 lost - In this case, we wont be here */ - /* 3 - Both L1 and L2 lost */ - ldr r1, pm_pwstctrl_mpu - ldr r2, [r1] - and r2, r2, #0x3 - cmp r2, #0x0 @ Check if target power state was OFF or RET - moveq r9, #0x3 @ MPU OFF => L1 and L2 lost - movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation - bne logic_l1_restore - /* Execute smi to invalidate L2 cache */ - mov r12, #0x1 @ set up to invalide L2 -smi: .word 0xE1600070 @ Call SMI monitor (smieq) -logic_l1_restore: - mov r1, #0 - /* Invalidate all instruction caches to PoU - * and flush branch target cache */ - mcr p15, 0, r1, c7, c5, 0 - - ldr r4, scratchpad_base - ldr r3, [r4,#0xBC] - ldmia r3!, {r4-r6} - mov sp, r4 - msr spsr_cxsf, r5 - mov lr, r6 - - ldmia r3!, {r4-r9} - /* Coprocessor access Control Register */ - mcr p15, 0, r4, c1, c0, 2 - - /* TTBR0 */ - MCR p15, 0, r5, c2, c0, 0 - /* TTBR1 */ - MCR p15, 0, r6, c2, c0, 1 - /* Translation table base control register */ - MCR p15, 0, r7, c2, c0, 2 - /*domain access Control Register */ - MCR p15, 0, r8, c3, c0, 0 - /* data fault status Register */ - MCR p15, 0, r9, c5, c0, 0 - - ldmia r3!,{r4-r8} - /* instruction fault status Register */ - MCR p15, 0, r4, c5, c0, 1 - /*Data Auxiliary Fault Status Register */ - MCR p15, 0, r5, c5, c1, 0 - /*Instruction Auxiliary Fault Status Register*/ - MCR p15, 0, r6, c5, c1, 1 - /*Data Fault Address Register */ - MCR p15, 0, r7, c6, c0, 0 - /*Instruction Fault Address Register*/ - MCR p15, 0, r8, c6, c0, 2 - ldmia r3!,{r4-r7} - - /* user r/w thread and process ID */ - MCR p15, 0, r4, c13, c0, 2 - /* user ro thread and process ID */ - MCR p15, 0, r5, c13, c0, 3 - /*Privileged only thread and process ID */ - MCR p15, 0, r6, c13, c0, 4 - /* cache size selection */ - MCR p15, 2, r7, c0, c0, 0 - ldmia r3!,{r4-r8} - /* Data TLB lockdown registers */ - MCR p15, 0, r4, c10, c0, 0 - /* Instruction TLB lockdown registers */ - MCR p15, 0, r5, c10, c0, 1 - /* Secure or Nonsecure Vector Base Address */ - MCR p15, 0, r6, c12, c0, 0 - /* FCSE PID */ - MCR p15, 0, r7, c13, c0, 0 - /* Context PID */ - MCR p15, 0, r8, c13, c0, 1 - - ldmia r3!,{r4-r5} - /* primary memory remap register */ - MCR p15, 0, r4, c10, c2, 0 - /*normal memory remap register */ - MCR p15, 0, r5, c10, c2, 1 - - /* Restore registers for other modes from SDRAM */ - /* Save current mode */ - mrs r7, cpsr - - /* FIQ mode */ - bic r0, r7, #0x1F - orr r0, r0, #0x11 - msr cpsr, r0 - ldmia r3!, {r8-r12} - /* load the SP and LR from SDRAM */ - ldmia r3!,{r4-r6} - mov sp, r4 /*update the SP */ - mov lr, r5 /*update the LR */ - msr spsr, r6 /*update the SPSR*/ - - /* IRQ mode */ - bic r0, r7, #0x1F - orr r0, r0, #0x12 - msr cpsr, r0 /*go into IRQ mode*/ - ldmia r3!,{r4-r6} /*load the SP and LR from SDRAM*/ - mov sp, r4 /*update the SP */ - mov lr, r5 /*update the LR */ - msr spsr, r6 /*update the SPSR */ - - /* ABORT mode */ - bic r0, r7, #0x1F - orr r0, r0, #0x17 - msr cpsr, r0 /* go into ABORT mode */ - ldmia r3!,{r4-r6} /*load the SP and LR from SDRAM */ - mov sp, r4 /*update the SP */ - mov lr, r5 /*update the LR */ - msr spsr, r6 /*update the SPSR */ - - /* UNDEEF mode */ - bic r0, r7, #0x1F - orr r0, r0, #0x1B - msr cpsr, r0 /*go into UNDEF mode */ - ldmia r3!,{r4-r6} /*load the SP and LR from SDRAM */ - mov sp, r4 /*update the SP*/ - mov lr, r5 /*update the LR*/ - msr spsr, r6 /*update the SPSR*/ - - /* SYSTEM (USER) mode */ - bic r0, r7, #0x1F - orr r0, r0, #0x1F - msr cpsr, r0 /*go into USR mode */ - ldmia r3!,{r4-r6} /*load the SP and LR from SDRAM*/ - mov sp, r4 /*update the SP */ - mov lr, r5 /*update the LR */ - msr spsr, r6 /*update the SPSR */ - msr cpsr, r7 /*back to original mode*/ - - /* Restore cpsr */ - ldmia r3!,{r4} /*load CPSR from SDRAM*/ - msr cpsr, r4 /*store cpsr */ - - /* Enabling MMU here */ - mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */ - /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/ - and r7, #0x7 - cmp r7, #0x0 - beq usettbr0 -ttbr_error: - /* More work needs to be done to support N[0:2] value other than 0 - * So looping here so that the error can be detected - */ - b ttbr_error -usettbr0: - mrc p15, 0, r2, c2, c0, 0 - ldr r5, ttbrbit_mask - and r2, r5 - mov r4, pc - ldr r5, table_index_mask - and r4, r5 /* r4 = 31 to 20 bits of pc */ - /* Extract the value to be written to table entry */ - ldr r1, table_entry - add r1, r1, r4 /* r1 has value to be written to table entry*/ - /* Getting the address of table entry to modify */ - lsr r4, #18 - add r2, r4 /* r2 has the location which needs to be modified */ - /* Storing previous entry of location being modified */ - ldr r5, scratchpad_base - ldr r4, [r2] - str r4, [r5, #0xC0] - /* Modify the table entry */ - str r1, [r2] - /* Storing address of entry being modified - * - will be restored after enabling MMU */ - ldr r5, scratchpad_base - str r2, [r5, #0xC4] - - mov r0, #0 - mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer - mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array - mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB - mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB - /* Restore control register but dont enable caches here*/ - /* Caches will be enabled after restoring MMU table entry */ - ldmia r3!, {r4} - /* Store previous value of control register in scratchpad */ - str r4, [r5, #0xC8] - ldr r2, cache_pred_disable_mask - and r4, r2 - mcr p15, 0, r4, c1, c0, 0 - - ldmfd sp!, {r0-r12, pc} @ restore regs and return -save_context_wfi: - /*b save_context_wfi*/ @ enable to debug save code - mov r8, r0 /* Store SDRAM address in r8 */ - /* Check what that target sleep state is:stored in r1*/ - /* 1 - Only L1 and logic lost */ - /* 2 - Only L2 lost */ - /* 3 - Both L1 and L2 lost */ - cmp r1, #0x2 /* Only L2 lost */ - beq clean_l2 - cmp r1, #0x1 /* L2 retained */ - /* r9 stores whether to clean L2 or not*/ - moveq r9, #0x0 /* Dont Clean L2 */ - movne r9, #0x1 /* Clean L2 */ -l1_logic_lost: - /* Store sp and spsr to SDRAM */ - mov r4, sp - mrs r5, spsr - mov r6, lr - stmia r8!, {r4-r6} - /* Save all ARM registers */ - /* Coprocessor access control register */ - mrc p15, 0, r6, c1, c0, 2 - stmia r8!, {r6} - /* TTBR0, TTBR1 and Translation table base control */ - mrc p15, 0, r4, c2, c0, 0 - mrc p15, 0, r5, c2, c0, 1 - mrc p15, 0, r6, c2, c0, 2 - stmia r8!, {r4-r6} - /* Domain access control register, data fault status register, - and instruction fault status register */ - mrc p15, 0, r4, c3, c0, 0 - mrc p15, 0, r5, c5, c0, 0 - mrc p15, 0, r6, c5, c0, 1 - stmia r8!, {r4-r6} - /* Data aux fault status register, instruction aux fault status, - datat fault address register and instruction fault address register*/ - mrc p15, 0, r4, c5, c1, 0 - mrc p15, 0, r5, c5, c1, 1 - mrc p15, 0, r6, c6, c0, 0 - mrc p15, 0, r7, c6, c0, 2 - stmia r8!, {r4-r7} - /* user r/w thread and process ID, user r/o thread and process ID, - priv only thread and process ID, cache size selection */ - mrc p15, 0, r4, c13, c0, 2 - mrc p15, 0, r5, c13, c0, 3 - mrc p15, 0, r6, c13, c0, 4 - mrc p15, 2, r7, c0, c0, 0 - stmia r8!, {r4-r7} - /* Data TLB lockdown, instruction TLB lockdown registers */ - mrc p15, 0, r5, c10, c0, 0 - mrc p15, 0, r6, c10, c0, 1 - stmia r8!, {r5-r6} - /* Secure or non secure vector base address, FCSE PID, Context PID*/ - mrc p15, 0, r4, c12, c0, 0 - mrc p15, 0, r5, c13, c0, 0 - mrc p15, 0, r6, c13, c0, 1 - stmia r8!, {r4-r6} - /* Primary remap, normal remap registers */ - mrc p15, 0, r4, c10, c2, 0 - mrc p15, 0, r5, c10, c2, 1 - stmia r8!,{r4-r5} - /* Store SP, LR, SPSR registers for SUP, FIQ, IRQ, ABORT and USER - modes into SDRAM */ - - /* move SDRAM address to r7 as r8 is banked in FIQ*/ - mov r7, r8 - - /* Save current mode */ - mrs r2, cpsr - /* FIQ mode */ - bic r0, r2, #0x1F - orr r0, r0, #0x11 - msr cpsr, r0 /* go to FIQ mode */ - stmia r7!, {r8-r12} - mov r4, r13 /* move SP into r4*/ - mov r5, r14 - mrs r6, spsr - stmia r7!, {r4-r6} - - /* IRQ mode */ - bic r0, r2, #0x1F - orr r0, r0, #0x12 - msr cpsr, r0 - mov r4, r13 - mov r5, r14 - mrs r6, spsr - stmia r7!, {r4-r6} - - /* Abort mode */ - bic r0, r2, #0x1F - orr r0, r0, #0x17 - msr cpsr, r0 - mov r4, r13 - mov r5, r14 - mrs r6, spsr - stmia r7!, {r4-r6} - - /* UNDEF mode */ - bic r0, r2, #0x1F - orr r0, r0, #0x1B - msr cpsr, r0 - mov r4, r13 - mov r5, r14 - mrs r6, spsr - stmia r7!, {r4-r6} - - /* System (USER mode) */ - bic r0, r2, #0x1F - orr r0, r0, #0x1F - msr cpsr, r0 - mov r4, r13 - mov r5, r14 - mrs r6, spsr - stmia r7!, {r4-r6} - - /* Back to original mode */ - msr cpsr, r2 - - /* Store current cpsr*/ - stmia r7!, {r2} - - mrc p15, 0, r4, c1, c0, 0 - /* save control register */ - stmia r7!, {r4} -clean_caches: - /* Clean Data or unified cache to POU*/ - /* How to invalidate only L1 cache???? - #FIX_ME# */ - /* mcr p15, 0, r11, c7, c11, 1 */ - cmp r9, #1 /* Check whether L2 inval is required or not*/ - bne skip_l2_inval -clean_l2: - /* read clidr */ - mrc p15, 1, r0, c0, c0, 1 - /* extract loc from clidr */ - ands r3, r0, #0x7000000 - /* left align loc bit field */ - mov r3, r3, lsr #23 - /* if loc is 0, then no need to clean */ - beq finished - /* start clean at cache level 0 */ - mov r10, #0 -loop1: - /* work out 3x current cache level */ - add r2, r10, r10, lsr #1 - /* extract cache type bits from clidr*/ - mov r1, r0, lsr r2 - /* mask of the bits for current cache only */ - and r1, r1, #7 - /* see what cache we have at this level */ - cmp r1, #2 - /* skip if no cache, or just i-cache */ - blt skip - /* select current cache level in cssr */ - mcr p15, 2, r10, c0, c0, 0 - /* isb to sych the new cssr&csidr */ - isb - /* read the new csidr */ - mrc p15, 1, r1, c0, c0, 0 - /* extract the length of the cache lines */ - and r2, r1, #7 - /* add 4 (line length offset) */ - add r2, r2, #4 - ldr r4, assoc_mask - /* find maximum number on the way size */ - ands r4, r4, r1, lsr #3 - /* find bit position of way size increment */ - clz r5, r4 - ldr r7, numset_mask - /* extract max number of the index size*/ - ands r7, r7, r1, lsr #13 -loop2: - mov r9, r4 - /* create working copy of max way size*/ -loop3: - /* factor way and cache number into r11 */ - orr r11, r10, r9, lsl r5 - /* factor index number into r11 */ - orr r11, r11, r7, lsl r2 - /*clean & invalidate by set/way */ - mcr p15, 0, r11, c7, c10, 2 - /* decrement the way*/ - subs r9, r9, #1 - bge loop3 - /*decrement the index */ - subs r7, r7, #1 - bge loop2 -skip: - add r10, r10, #2 - /* increment cache number */ - cmp r3, r10 - bgt loop1 -finished: - /*swith back to cache level 0 */ - mov r10, #0 - /* select current cache level in cssr */ - mcr p15, 2, r10, c0, c0, 0 - isb -skip_l2_inval: - /* Data memory barrier and Data sync barrier */ - mov r1, #0 - mcr p15, 0, r1, c7, c10, 4 - mcr p15, 0, r1, c7, c10, 5 - - wfi @ wait for interrupt - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - bl i_dll_wait - /* restore regs and return */ - ldmfd sp!, {r0-r12, pc} - -i_dll_wait: - ldr r4, clk_stabilize_delay - -i_dll_delay: - subs r4, r4, #0x1 - bne i_dll_delay - ldr r4, sdrc_power - ldr r5, [r4] - bic r5, r5, #0x40 - str r5, [r4] - bx lr -pm_prepwstst_core: - .word PM_PREPWSTST_CORE_V -pm_prepwstst_mpu: - .word PM_PREPWSTST_MPU_V -pm_pwstctrl_mpu: - .word PM_PWSTCTRL_MPU_P -scratchpad_base: - .word SCRATCHPAD_BASE_P -sdrc_power: - .word SDRC_POWER_V -context_mem: - .word 0x803E3E14 -clk_stabilize_delay: - .word 0x000001FF -assoc_mask: - .word 0x3ff -numset_mask: - .word 0x7fff -ttbrbit_mask: - .word 0xFFFFC000 -table_index_mask: - .word 0xFFF00000 -table_entry: - .word 0x00000C02 -cache_pred_disable_mask: - .word 0xFFFFE7FB -ENTRY(omap34xx_cpu_suspend_sz) - .word . - omap34xx_cpu_suspend diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c deleted file mode 100644 index f26a9a1831f..00000000000 --- a/arch/arm/mach-omap2/smartreflex.c +++ /dev/null @@ -1,762 +0,0 @@ -/* - * linux/arch/arm/mach-omap3/smartreflex.c - * - * OMAP34XX SmartReflex Voltage Control - * - * Copyright (C) 2008 Nokia Corporation - * Kalle Jokiniemi - * - * Copyright (C) 2007 Texas Instruments, Inc. - * Lesly A M - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "prm.h" -#include "smartreflex.h" -#include "prm-regbits-34xx.h" - -/* XXX: These should be relocated where-ever the OPP implementation will be */ -u32 current_vdd1_opp; -u32 current_vdd2_opp; - -struct omap_sr { - int srid; - int is_sr_reset; - int is_autocomp_active; - struct clk *clk; - u32 clk_length; - u32 req_opp_no; - u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue; - u32 opp5_nvalue; - u32 senp_mod, senn_mod; - void __iomem *srbase_addr; - void __iomem *vpbase_addr; -}; - -#define SR_REGADDR(offs) (sr->srbase_addr + offset) - -static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value) -{ - __raw_writel(value, SR_REGADDR(offset)); -} - -static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask, - u32 value) -{ - u32 reg_val; - - reg_val = __raw_readl(SR_REGADDR(offset)); - reg_val &= ~mask; - reg_val |= value; - - __raw_writel(reg_val, SR_REGADDR(offset)); -} - -static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset) -{ - return __raw_readl(SR_REGADDR(offset)); -} - -static int sr_clk_enable(struct omap_sr *sr) -{ - if (clk_enable(sr->clk) != 0) { - printk(KERN_ERR "Could not enable %s\n", sr->clk->name); - return -1; - } - - /* set fclk- active , iclk- idle */ - sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK, - SR_CLKACTIVITY_IOFF_FON); - - return 0; -} - -static void sr_clk_disable(struct omap_sr *sr) -{ - /* set fclk, iclk- idle */ - sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK, - SR_CLKACTIVITY_IOFF_FOFF); - - clk_disable(sr->clk); - sr->is_sr_reset = 1; -} - -static struct omap_sr sr1 = { - .srid = SR1, - .is_sr_reset = 1, - .is_autocomp_active = 0, - .clk_length = 0, - .srbase_addr = OMAP2_IO_ADDRESS(OMAP34XX_SR1_BASE), -}; - -static struct omap_sr sr2 = { - .srid = SR2, - .is_sr_reset = 1, - .is_autocomp_active = 0, - .clk_length = 0, - .srbase_addr = OMAP2_IO_ADDRESS(OMAP34XX_SR2_BASE), -}; - -static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen) -{ - u32 gn, rn, mul; - - for (gn = 0; gn < GAIN_MAXLIMIT; gn++) { - mul = 1 << (gn + 8); - rn = mul / sensor; - if (rn < R_MAXLIMIT) { - *sengain = gn; - *rnsen = rn; - } - } -} - -static u32 cal_test_nvalue(u32 sennval, u32 senpval) -{ - u32 senpgain, senngain; - u32 rnsenp, rnsenn; - - /* Calculating the gain and reciprocal of the SenN and SenP values */ - cal_reciprocal(senpval, &senpgain, &rnsenp); - cal_reciprocal(sennval, &senngain, &rnsenn); - - return ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | - (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | - (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | - (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -} - -static void sr_set_clk_length(struct omap_sr *sr) -{ - struct clk *osc_sys_ck; - u32 sys_clk = 0; - - osc_sys_ck = clk_get(NULL, "osc_sys_ck"); - sys_clk = clk_get_rate(osc_sys_ck); - clk_put(osc_sys_ck); - - switch (sys_clk) { - case 12000000: - sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK; - break; - case 13000000: - sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK; - break; - case 19200000: - sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK; - break; - case 26000000: - sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK; - break; - case 38400000: - sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK; - break; - default : - printk(KERN_ERR "Invalid sysclk value: %d\n", sys_clk); - break; - } -} - -static void sr_set_efuse_nvalues(struct omap_sr *sr) -{ - if (sr->srid == SR1) { - sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & - OMAP343X_SR1_SENNENABLE_MASK) >> - OMAP343X_SR1_SENNENABLE_SHIFT; - - sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & - OMAP343X_SR1_SENPENABLE_MASK) >> - OMAP343X_SR1_SENPENABLE_SHIFT; - - sr->opp5_nvalue = omap_ctrl_readl( - OMAP343X_CONTROL_FUSE_OPP5_VDD1); - sr->opp4_nvalue = omap_ctrl_readl( - OMAP343X_CONTROL_FUSE_OPP4_VDD1); - sr->opp3_nvalue = omap_ctrl_readl( - OMAP343X_CONTROL_FUSE_OPP3_VDD1); - sr->opp2_nvalue = omap_ctrl_readl( - OMAP343X_CONTROL_FUSE_OPP2_VDD1); - sr->opp1_nvalue = omap_ctrl_readl( - OMAP343X_CONTROL_FUSE_OPP1_VDD1); - } else if (sr->srid == SR2) { - sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & - OMAP343X_SR2_SENNENABLE_MASK) >> - OMAP343X_SR2_SENNENABLE_SHIFT; - - sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & - OMAP343X_SR2_SENPENABLE_MASK) >> - OMAP343X_SR2_SENPENABLE_SHIFT; - - sr->opp3_nvalue = omap_ctrl_readl( - OMAP343X_CONTROL_FUSE_OPP3_VDD2); - sr->opp2_nvalue = omap_ctrl_readl( - OMAP343X_CONTROL_FUSE_OPP2_VDD2); - sr->opp1_nvalue = omap_ctrl_readl( - OMAP343X_CONTROL_FUSE_OPP1_VDD2); - } -} - -/* Hard coded nvalues for testing purposes, may cause device to hang! */ -static void sr_set_testing_nvalues(struct omap_sr *sr) -{ - if (sr->srid == SR1) { - sr->senp_mod = 0x03; /* SenN-M5 enabled */ - sr->senn_mod = 0x03; - - /* calculate nvalues for each opp */ - sr->opp5_nvalue = cal_test_nvalue(0xacd + 0x330, 0x848 + 0x330); - sr->opp4_nvalue = cal_test_nvalue(0x964 + 0x2a0, 0x727 + 0x2a0); - sr->opp3_nvalue = cal_test_nvalue(0x85b + 0x200, 0x655 + 0x200); - sr->opp2_nvalue = cal_test_nvalue(0x506 + 0x1a0, 0x3be + 0x1a0); - sr->opp1_nvalue = cal_test_nvalue(0x373 + 0x100, 0x28c + 0x100); - } else if (sr->srid == SR2) { - sr->senp_mod = 0x03; - sr->senn_mod = 0x03; - - sr->opp3_nvalue = cal_test_nvalue(0x76f + 0x200, 0x579 + 0x200); - sr->opp2_nvalue = cal_test_nvalue(0x4f5 + 0x1c0, 0x390 + 0x1c0); - sr->opp1_nvalue = cal_test_nvalue(0x359, 0x25d); - } - -} - -static void sr_set_nvalues(struct omap_sr *sr) -{ - if (SR_TESTING_NVALUES) - sr_set_testing_nvalues(sr); - else - sr_set_efuse_nvalues(sr); -} - -static void sr_configure_vp(int srid) -{ - u32 vpconfig; - - if (srid == SR1) { - vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN - | PRM_VP1_CONFIG_INITVOLTAGE - | PRM_VP1_CONFIG_TIMEOUTEN; - - prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD, - OMAP3_PRM_VP1_CONFIG_OFFSET); - prm_write_mod_reg(PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN | - PRM_VP1_VSTEPMIN_VSTEPMIN, - OMAP3430_GR_MOD, - OMAP3_PRM_VP1_VSTEPMIN_OFFSET); - - prm_write_mod_reg(PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX | - PRM_VP1_VSTEPMAX_VSTEPMAX, - OMAP3430_GR_MOD, - OMAP3_PRM_VP1_VSTEPMAX_OFFSET); - - prm_write_mod_reg(PRM_VP1_VLIMITTO_VDDMAX | - PRM_VP1_VLIMITTO_VDDMIN | - PRM_VP1_VLIMITTO_TIMEOUT, - OMAP3430_GR_MOD, - OMAP3_PRM_VP1_VLIMITTO_OFFSET); - - /* Trigger initVDD value copy to voltage processor */ - prm_set_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD, - OMAP3_PRM_VP1_CONFIG_OFFSET); - /* Clear initVDD copy trigger bit */ - prm_clear_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD, - OMAP3_PRM_VP1_CONFIG_OFFSET); - - } else if (srid == SR2) { - vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN - | PRM_VP2_CONFIG_INITVOLTAGE - | PRM_VP2_CONFIG_TIMEOUTEN; - - prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD, - OMAP3_PRM_VP2_CONFIG_OFFSET); - prm_write_mod_reg(PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN | - PRM_VP2_VSTEPMIN_VSTEPMIN, - OMAP3430_GR_MOD, - OMAP3_PRM_VP2_VSTEPMIN_OFFSET); - - prm_write_mod_reg(PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX | - PRM_VP2_VSTEPMAX_VSTEPMAX, - OMAP3430_GR_MOD, - OMAP3_PRM_VP2_VSTEPMAX_OFFSET); - - prm_write_mod_reg(PRM_VP2_VLIMITTO_VDDMAX | - PRM_VP2_VLIMITTO_VDDMIN | - PRM_VP2_VLIMITTO_TIMEOUT, - OMAP3430_GR_MOD, - OMAP3_PRM_VP2_VLIMITTO_OFFSET); - - /* Trigger initVDD value copy to voltage processor */ - prm_set_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD, - OMAP3_PRM_VP2_CONFIG_OFFSET); - /* Reset initVDD copy trigger bit */ - prm_clear_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD, - OMAP3_PRM_VP2_CONFIG_OFFSET); - - } -} - -static void sr_configure(struct omap_sr *sr) -{ - u32 sr_config; - u32 senp_en , senn_en; - - if (sr->clk_length == 0) - sr_set_clk_length(sr); - - senp_en = sr->senp_mod; - senn_en = sr->senn_mod; - if (sr->srid == SR1) { - sr_config = SR1_SRCONFIG_ACCUMDATA | - (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | - SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN | - SRCONFIG_MINMAXAVG_EN | - (senn_en << SRCONFIG_SENNENABLE_SHIFT) | - (senp_en << SRCONFIG_SENPENABLE_SHIFT) | - SRCONFIG_DELAYCTRL; - - sr_write_reg(sr, SRCONFIG, sr_config); - sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT | - SR1_AVGWEIGHT_SENNAVGWEIGHT); - - sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK | - SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), - (SR1_ERRWEIGHT | SR1_ERRMAXLIMIT | SR1_ERRMINLIMIT)); - - } else if (sr->srid == SR2) { - sr_config = SR2_SRCONFIG_ACCUMDATA | - (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | - SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN | - SRCONFIG_MINMAXAVG_EN | - (senn_en << SRCONFIG_SENNENABLE_SHIFT) | - (senp_en << SRCONFIG_SENPENABLE_SHIFT) | - SRCONFIG_DELAYCTRL; - - sr_write_reg(sr, SRCONFIG, sr_config); - sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT | - SR2_AVGWEIGHT_SENNAVGWEIGHT); - sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK | - SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), - (SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT)); - - } - sr->is_sr_reset = 0; -} - -static int sr_enable(struct omap_sr *sr, u32 target_opp_no) -{ - u32 nvalue_reciprocal; - - sr->req_opp_no = target_opp_no; - - if (sr->srid == SR1) { - switch (target_opp_no) { - case 5: - nvalue_reciprocal = sr->opp5_nvalue; - break; - case 4: - nvalue_reciprocal = sr->opp4_nvalue; - break; - case 3: - nvalue_reciprocal = sr->opp3_nvalue; - break; - case 2: - nvalue_reciprocal = sr->opp2_nvalue; - break; - case 1: - nvalue_reciprocal = sr->opp1_nvalue; - break; - default: - nvalue_reciprocal = sr->opp3_nvalue; - break; - } - } else { - switch (target_opp_no) { - case 3: - nvalue_reciprocal = sr->opp3_nvalue; - break; - case 2: - nvalue_reciprocal = sr->opp2_nvalue; - break; - case 1: - nvalue_reciprocal = sr->opp1_nvalue; - break; - default: - nvalue_reciprocal = sr->opp3_nvalue; - break; - } - } - - if (nvalue_reciprocal == 0) { - printk(KERN_NOTICE "OPP%d doesn't support SmartReflex\n", - target_opp_no); - return SR_FALSE; - } - - sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal); - - /* Enable the interrupt */ - sr_modify_reg(sr, ERRCONFIG, - (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST), - (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST)); - if (sr->srid == SR1) { - /* Enable VP1 */ - prm_set_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD, - OMAP3_PRM_VP1_CONFIG_OFFSET); - } else if (sr->srid == SR2) { - /* Enable VP2 */ - prm_set_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD, - OMAP3_PRM_VP2_CONFIG_OFFSET); - } - - /* SRCONFIG - enable SR */ - sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE); - return SR_TRUE; -} - -static void sr_disable(struct omap_sr *sr) -{ - sr->is_sr_reset = 1; - - /* SRCONFIG - disable SR */ - sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE); - - if (sr->srid == SR1) { - /* Disable VP1 */ - prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD, - OMAP3_PRM_VP1_CONFIG_OFFSET); - } else if (sr->srid == SR2) { - /* Disable VP2 */ - prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD, - OMAP3_PRM_VP2_CONFIG_OFFSET); - } -} - - -void sr_start_vddautocomap(int srid, u32 target_opp_no) -{ - struct omap_sr *sr = NULL; - - if (srid == SR1) - sr = &sr1; - else if (srid == SR2) - sr = &sr2; - - if (sr->is_sr_reset == 1) { - sr_clk_enable(sr); - sr_configure(sr); - } - - if (sr->is_autocomp_active == 1) - printk(KERN_WARNING "SR%d: VDD autocomp is already active\n", - srid); - - sr->is_autocomp_active = 1; - if (!sr_enable(sr, target_opp_no)) { - printk(KERN_WARNING "SR%d: VDD autocomp not activated\n", srid); - sr->is_autocomp_active = 0; - if (sr->is_sr_reset == 1) - sr_clk_disable(sr); - } -} -EXPORT_SYMBOL(sr_start_vddautocomap); - -int sr_stop_vddautocomap(int srid) -{ - struct omap_sr *sr = NULL; - - if (srid == SR1) - sr = &sr1; - else if (srid == SR2) - sr = &sr2; - - if (sr->is_autocomp_active == 1) { - sr_disable(sr); - sr_clk_disable(sr); - sr->is_autocomp_active = 0; - return SR_TRUE; - } else { - printk(KERN_WARNING "SR%d: VDD autocomp is not active\n", - srid); - return SR_FALSE; - } - -} -EXPORT_SYMBOL(sr_stop_vddautocomap); - -void enable_smartreflex(int srid) -{ - u32 target_opp_no = 0; - struct omap_sr *sr = NULL; - - if (srid == SR1) - sr = &sr1; - else if (srid == SR2) - sr = &sr2; - - if (sr->is_autocomp_active == 1) { - if (sr->is_sr_reset == 1) { - /* Enable SR clks */ - sr_clk_enable(sr); - - if (srid == SR1) - target_opp_no = get_opp_no(current_vdd1_opp); - else if (srid == SR2) - target_opp_no = get_opp_no(current_vdd2_opp); - - sr_configure(sr); - - if (!sr_enable(sr, target_opp_no)) - sr_clk_disable(sr); - } - } -} - -void disable_smartreflex(int srid) -{ - struct omap_sr *sr = NULL; - - if (srid == SR1) - sr = &sr1; - else if (srid == SR2) - sr = &sr2; - - if (sr->is_autocomp_active == 1) { - if (sr->is_sr_reset == 0) { - - sr->is_sr_reset = 1; - /* SRCONFIG - disable SR */ - sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, - ~SRCONFIG_SRENABLE); - - /* Disable SR clk */ - sr_clk_disable(sr); - if (sr->srid == SR1) { - /* Disable VP1 */ - prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, - OMAP3430_GR_MOD, - OMAP3_PRM_VP1_CONFIG_OFFSET); - } else if (sr->srid == SR2) { - /* Disable VP2 */ - prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, - OMAP3430_GR_MOD, - OMAP3_PRM_VP2_CONFIG_OFFSET); - } - } - } -} - -/* Voltage Scaling using SR VCBYPASS */ -int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel) -{ - int sr_status = 0; - u32 vdd, target_opp_no; - u32 vc_bypass_value; - u32 reg_addr = 0; - u32 loop_cnt = 0, retries_cnt = 0; - - vdd = get_vdd(target_opp); - target_opp_no = get_opp_no(target_opp); - - if (vdd == PRCM_VDD1) { - sr_status = sr_stop_vddautocomap(SR1); - - prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK, - (vsel << OMAP3430_VC_CMD_ON_SHIFT), - OMAP3430_GR_MOD, - OMAP3_PRM_VC_CMD_VAL_0_OFFSET); - reg_addr = R_VDD1_SR_CONTROL; - - } else if (vdd == PRCM_VDD2) { - sr_status = sr_stop_vddautocomap(SR2); - - prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK, - (vsel << OMAP3430_VC_CMD_ON_SHIFT), - OMAP3430_GR_MOD, - OMAP3_PRM_VC_CMD_VAL_1_OFFSET); - reg_addr = R_VDD2_SR_CONTROL; - } - - vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) | - (reg_addr << OMAP3430_REGADDR_SHIFT) | - (R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT); - - prm_write_mod_reg(vc_bypass_value, OMAP3430_GR_MOD, - OMAP3_PRM_VC_BYPASS_VAL_OFFSET); - - vc_bypass_value = prm_set_mod_reg_bits(OMAP3430_VALID, OMAP3430_GR_MOD, - OMAP3_PRM_VC_BYPASS_VAL_OFFSET); - - while ((vc_bypass_value & OMAP3430_VALID) != 0x0) { - loop_cnt++; - if (retries_cnt > 10) { - printk(KERN_INFO "Loop count exceeded in check SR I2C" - "write\n"); - return SR_FAIL; - } - if (loop_cnt > 50) { - retries_cnt++; - loop_cnt = 0; - udelay(10); - } - vc_bypass_value = prm_read_mod_reg(OMAP3430_GR_MOD, - OMAP3_PRM_VC_BYPASS_VAL_OFFSET); - } - - udelay(T2_SMPS_UPDATE_DELAY); - - if (sr_status) { - if (vdd == PRCM_VDD1) - sr_start_vddautocomap(SR1, target_opp_no); - else if (vdd == PRCM_VDD2) - sr_start_vddautocomap(SR2, target_opp_no); - } - - return SR_PASS; -} - -/* Sysfs interface to select SR VDD1 auto compensation */ -static ssize_t omap_sr_vdd1_autocomp_show(struct kobject *kobj, - struct kobj_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", sr1.is_autocomp_active); -} - -static ssize_t omap_sr_vdd1_autocomp_store(struct kobject *kobj, - struct kobj_attribute *attr, - const char *buf, size_t n) -{ - u32 current_vdd1opp_no; - unsigned short value; - - if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) { - printk(KERN_ERR "sr_vdd1_autocomp: Invalid value\n"); - return -EINVAL; - } - - current_vdd1opp_no = get_opp_no(current_vdd1_opp); - - if (value == 0) - sr_stop_vddautocomap(SR1); - else - sr_start_vddautocomap(SR1, current_vdd1opp_no); - - return n; -} - -static struct kobj_attribute sr_vdd1_autocomp = { - .attr = { - .name = __stringify(sr_vdd1_autocomp), - .mode = 0644, - }, - .show = omap_sr_vdd1_autocomp_show, - .store = omap_sr_vdd1_autocomp_store, -}; - -/* Sysfs interface to select SR VDD2 auto compensation */ -static ssize_t omap_sr_vdd2_autocomp_show(struct kobject *kobj, - struct kobj_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", sr2.is_autocomp_active); -} - -static ssize_t omap_sr_vdd2_autocomp_store(struct kobject *kobj, - struct kobj_attribute *attr, - const char *buf, size_t n) -{ - u32 current_vdd2opp_no; - unsigned short value; - - if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) { - printk(KERN_ERR "sr_vdd2_autocomp: Invalid value\n"); - return -EINVAL; - } - - current_vdd2opp_no = get_opp_no(current_vdd2_opp); - - if (value == 0) - sr_stop_vddautocomap(SR2); - else - sr_start_vddautocomap(SR2, current_vdd2opp_no); - - return n; -} - -static struct kobj_attribute sr_vdd2_autocomp = { - .attr = { - .name = __stringify(sr_vdd2_autocomp), - .mode = 0644, - }, - .show = omap_sr_vdd2_autocomp_show, - .store = omap_sr_vdd2_autocomp_store, -}; - - - -static int __init omap3_sr_init(void) -{ - int ret = 0; - u8 RdReg; - - if (omap_rev() > OMAP3430_REV_ES1_0) { - current_vdd1_opp = PRCM_VDD1_OPP3; - current_vdd2_opp = PRCM_VDD2_OPP3; - } else { - current_vdd1_opp = PRCM_VDD1_OPP1; - current_vdd2_opp = PRCM_VDD1_OPP1; - } - if (cpu_is_omap34xx()) { - sr1.clk = clk_get(NULL, "sr1_fck"); - sr2.clk = clk_get(NULL, "sr2_fck"); - } - sr_set_clk_length(&sr1); - sr_set_clk_length(&sr2); - - /* Call the VPConfig, VCConfig, set N Values. */ - sr_set_nvalues(&sr1); - sr_configure_vp(SR1); - - sr_set_nvalues(&sr2); - sr_configure_vp(SR2); - - /* Enable SR on T2 */ - ret = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &RdReg, - R_DCDC_GLOBAL_CFG); - - RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX; - ret |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, RdReg, - R_DCDC_GLOBAL_CFG); - - printk(KERN_INFO "SmartReflex driver initialized\n"); - - ret = sysfs_create_file(power_kobj, &sr_vdd1_autocomp.attr); - if (ret) - printk(KERN_ERR "sysfs_create_file failed: %d\n", ret); - - ret = sysfs_create_file(power_kobj, &sr_vdd2_autocomp.attr); - if (ret) - printk(KERN_ERR "sysfs_create_file failed: %d\n", ret); - - return 0; -} - -late_initcall(omap3_sr_init); diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h deleted file mode 100644 index be6e6b9ec06..00000000000 --- a/arch/arm/mach-omap2/smartreflex.h +++ /dev/null @@ -1,259 +0,0 @@ -#ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H -#define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H -/* - * linux/arch/arm/mach-omap2/smartreflex.h - * - * Copyright (C) 2008 Nokia Corporation - * Kalle Jokiniemi - * - * Copyright (C) 2007 Texas Instruments, Inc. - * Lesly A M - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36) -#define PHY_TO_OFF_PM_RECIEVER(p) (p - 0x5b) -#define PHY_TO_OFF_PM_INT(p) (p - 0x2e) - -/* SMART REFLEX REG ADDRESS OFFSET */ -#define SRCONFIG 0x00 -#define SRSTATUS 0x04 -#define SENVAL 0x08 -#define SENMIN 0x0C -#define SENMAX 0x10 -#define SENAVG 0x14 -#define AVGWEIGHT 0x18 -#define NVALUERECIPROCAL 0x1C -#define SENERROR 0x20 -#define ERRCONFIG 0x24 - -/* SR Modules */ -#define SR1 1 -#define SR2 2 - -#define SR_FAIL 1 -#define SR_PASS 0 - -#define SR_TRUE 1 -#define SR_FALSE 0 - -#define GAIN_MAXLIMIT 16 -#define R_MAXLIMIT 256 - -#define SR1_CLK_ENABLE (0x1 << 6) -#define SR2_CLK_ENABLE (0x1 << 7) - -/* PRM_VP1_CONFIG */ -#define PRM_VP1_CONFIG_ERROROFFSET (0x00 << 24) -#define PRM_VP1_CONFIG_ERRORGAIN (0x20 << 16) - -#define PRM_VP1_CONFIG_INITVOLTAGE (0x30 << 8) /* 1.2 volt */ -#define PRM_VP1_CONFIG_TIMEOUTEN (0x1 << 3) -#define PRM_VP1_CONFIG_INITVDD (0x1 << 2) -#define PRM_VP1_CONFIG_FORCEUPDATE (0x1 << 1) -#define PRM_VP1_CONFIG_VPENABLE (0x1 << 0) - -/* PRM_VP1_VSTEPMIN */ -#define PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN (0x01F4 << 8) -#define PRM_VP1_VSTEPMIN_VSTEPMIN (0x01 << 0) - -/* PRM_VP1_VSTEPMAX */ -#define PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX (0x01F4 << 8) -#define PRM_VP1_VSTEPMAX_VSTEPMAX (0x04 << 0) - -/* PRM_VP1_VLIMITTO */ -#define PRM_VP1_VLIMITTO_VDDMAX (0x3C << 24) -#define PRM_VP1_VLIMITTO_VDDMIN (0x0 << 16) -#define PRM_VP1_VLIMITTO_TIMEOUT (0xFFFF << 0) - -/* PRM_VP2_CONFIG */ -#define PRM_VP2_CONFIG_ERROROFFSET (0x00 << 24) -#define PRM_VP2_CONFIG_ERRORGAIN (0x20 << 16) - -#define PRM_VP2_CONFIG_INITVOLTAGE (0x30 << 8) /* 1.2 volt */ -#define PRM_VP2_CONFIG_TIMEOUTEN (0x1 << 3) -#define PRM_VP2_CONFIG_INITVDD (0x1 << 2) -#define PRM_VP2_CONFIG_FORCEUPDATE (0x1 << 1) -#define PRM_VP2_CONFIG_VPENABLE (0x1 << 0) - -/* PRM_VP2_VSTEPMIN */ -#define PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN (0x01F4 << 8) -#define PRM_VP2_VSTEPMIN_VSTEPMIN (0x01 << 0) - -/* PRM_VP2_VSTEPMAX */ -#define PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX (0x01F4 << 8) -#define PRM_VP2_VSTEPMAX_VSTEPMAX (0x04 << 0) - -/* PRM_VP2_VLIMITTO */ -#define PRM_VP2_VLIMITTO_VDDMAX (0x2C << 24) -#define PRM_VP2_VLIMITTO_VDDMIN (0x0 << 16) -#define PRM_VP2_VLIMITTO_TIMEOUT (0xFFFF << 0) - -/* SRCONFIG */ -#define SR1_SRCONFIG_ACCUMDATA (0x1F4 << 22) -#define SR2_SRCONFIG_ACCUMDATA (0x1F4 << 22) - -#define SRCLKLENGTH_12MHZ_SYSCLK 0x3C -#define SRCLKLENGTH_13MHZ_SYSCLK 0x41 -#define SRCLKLENGTH_19MHZ_SYSCLK 0x60 -#define SRCLKLENGTH_26MHZ_SYSCLK 0x82 -#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0 - -#define SRCONFIG_SRCLKLENGTH_SHIFT 12 -#define SRCONFIG_SENNENABLE_SHIFT 5 -#define SRCONFIG_SENPENABLE_SHIFT 3 - -#define SRCONFIG_SRENABLE (0x01 << 11) -#define SRCONFIG_SENENABLE (0x01 << 10) -#define SRCONFIG_ERRGEN_EN (0x01 << 9) -#define SRCONFIG_MINMAXAVG_EN (0x01 << 8) - -#define SRCONFIG_DELAYCTRL (0x01 << 2) -#define SRCONFIG_CLKCTRL (0x00 << 0) - -/* AVGWEIGHT */ -#define SR1_AVGWEIGHT_SENPAVGWEIGHT (0x03 << 2) -#define SR1_AVGWEIGHT_SENNAVGWEIGHT (0x03 << 0) - -#define SR2_AVGWEIGHT_SENPAVGWEIGHT (0x01 << 2) -#define SR2_AVGWEIGHT_SENNAVGWEIGHT (0x01 << 0) - -/* NVALUERECIPROCAL */ -#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20 -#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16 -#define NVALUERECIPROCAL_RNSENP_SHIFT 8 -#define NVALUERECIPROCAL_RNSENN_SHIFT 0 - -/* ERRCONFIG */ -#define SR_CLKACTIVITY_MASK (0x03 << 20) -#define SR_ERRWEIGHT_MASK (0x07 << 16) -#define SR_ERRMAXLIMIT_MASK (0xFF << 8) -#define SR_ERRMINLIMIT_MASK (0xFF << 0) - -#define SR_CLKACTIVITY_IOFF_FOFF (0x00 << 20) -#define SR_CLKACTIVITY_IOFF_FON (0x02 << 20) - -#define ERRCONFIG_VPBOUNDINTEN (0x1 << 31) -#define ERRCONFIG_VPBOUNDINTST (0x1 << 30) - -#define SR1_ERRWEIGHT (0x07 << 16) -#define SR1_ERRMAXLIMIT (0x02 << 8) -#define SR1_ERRMINLIMIT (0xFA << 0) - -#define SR2_ERRWEIGHT (0x07 << 16) -#define SR2_ERRMAXLIMIT (0x02 << 8) -#define SR2_ERRMINLIMIT (0xF9 << 0) - -/* T2 SMART REFLEX */ -#define R_SRI2C_SLAVE_ADDR 0x12 -#define R_VDD1_SR_CONTROL 0x00 -#define R_VDD2_SR_CONTROL 0x01 -#define T2_SMPS_UPDATE_DELAY 360 /* In uSec */ - -/* Vmode control */ -#define R_DCDC_GLOBAL_CFG PHY_TO_OFF_PM_RECIEVER(0x61) - -#define R_VDD1_VSEL PHY_TO_OFF_PM_RECIEVER(0xb9) -#define R_VDD1_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xba) -#define R_VDD1_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xbb) -#define R_VDD1_VROOF PHY_TO_OFF_PM_RECIEVER(0xbc) -#define R_VDD1_STEP PHY_TO_OFF_PM_RECIEVER(0xbd) - -#define R_VDD2_VSEL PHY_TO_OFF_PM_RECIEVER(0xc7) -#define R_VDD2_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xc8) -#define R_VDD2_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xc9) -#define R_VDD2_VROOF PHY_TO_OFF_PM_RECIEVER(0xca) -#define R_VDD2_STEP PHY_TO_OFF_PM_RECIEVER(0xcb) - -/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE values */ -#define DCDC_GLOBAL_CFG_ENABLE_SRFLX 0x08 - -/* VDDs*/ -#define PRCM_VDD1 1 -#define PRCM_VDD2 2 -#define PRCM_MAX_SYSC_REGS 30 - -/* - * XXX: These should be removed/moved from here once we have a working DVFS - * implementation in place - */ -#define AT_3430 1 /*3430 ES 1.0 */ -#define AT_3430_ES2 2 /*3430 ES 2.0 */ - -#define ID_OPP 0xE2 /*OPP*/ - -/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */ -#define OMAP_TYPE_SHIFT 28 -#define OMAP_TYPE_MASK 0xF -/* OPP ID: bits: 0-4 for OPP number */ -#define OPP_NO_POS 0 -#define OPP_NO_MASK 0x1F -/* OPP ID: bits: 5-6 for VDD */ -#define VDD_NO_POS 5 -#define VDD_NO_MASK 0x3 -/* Other IDs: bits 20-27 for ID type */ -/* These IDs have bits 25,26,27 as 1 */ -#define OTHER_ID_TYPE_SHIFT 20 -#define OTHER_ID_TYPE_MASK 0xFF - -#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT) -#define ID_OPP_NO(X) ((X & OPP_NO_MASK) << OPP_NO_POS) -#define ID_VDD(X) ((X & VDD_NO_MASK) << VDD_NO_POS) -#define OMAP(X) ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK) -#define get_opp_no(X) ((X >> OPP_NO_POS) & OPP_NO_MASK) -#define get_vdd(X) ((X >> VDD_NO_POS) & VDD_NO_MASK) - -/* VDD1 OPPs */ -#define PRCM_VDD1_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ - ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1)) -#define PRCM_VDD1_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ - ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2)) -#define PRCM_VDD1_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ - ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3)) -#define PRCM_VDD1_OPP4 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ - ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4)) -#define PRCM_VDD1_OPP5 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ - ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5)) -#define PRCM_NO_VDD1_OPPS 5 - - -/* VDD2 OPPs */ -#define PRCM_VDD2_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ - ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1)) -#define PRCM_VDD2_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ - ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2)) -#define PRCM_VDD2_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ - ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3)) -#define PRCM_NO_VDD2_OPPS 3 -/* XXX: end remove/move */ - -/* XXX: find more appropriate place for these once DVFS is in place */ -extern u32 current_vdd1_opp; -extern u32 current_vdd2_opp; - -#ifdef CONFIG_OMAP_SMARTREFLEX_TESTING -#define SR_TESTING_NVALUES 1 -#else -#define SR_TESTING_NVALUES 0 -#endif - -/* - * Smartreflex module enable/disable interface. - * NOTE: if smartreflex is not enabled from sysfs, these functions will not - * do anything. - */ -#ifdef CONFIG_OMAP_SMARTREFLEX -void enable_smartreflex(int srid); -void disable_smartreflex(int srid); -int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel); -void sr_start_vddautocomap(int srid, u32 target_opp_no); -int sr_stop_vddautocomap(int srid); -#else -static inline void enable_smartreflex(int srid) {} -static inline void disable_smartreflex(int srid) {} -#endif - -#endif diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S index a2086c3804e..af4bd349022 100644 --- a/arch/arm/mach-omap2/sram242x.S +++ b/arch/arm/mach-omap2/sram242x.S @@ -31,11 +31,6 @@ #include "cm.h" #include "sdrc.h" -#define OMAP242X_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ - OMAP24XX_PRCM_VOLTCTRL_OFFSET) -#define OMAP242X_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ - OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) - .text ENTRY(omap242x_sram_ddr_init) diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index 7946a5ff58a..84363e269e8 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S @@ -31,11 +31,6 @@ #include "cm.h" #include "sdrc.h" -#define OMAP243X_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \ - OMAP24XX_PRCM_VOLTCTRL_OFFSET) -#define OMAP243X_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \ - OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) - .text ENTRY(omap243x_sram_ddr_init) diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index 8351a34f3e1..9fc13a2cc3f 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -99,7 +99,7 @@ static void __init omap2_gp_clockevent_init(void) { u32 tick_rate; - gptimer = omap_dm_timer_request_specific(CONFIG_OMAP_TICK_GPTIMER); + gptimer = omap_dm_timer_request_specific(1); BUG_ON(gptimer == NULL); #if defined(CONFIG_OMAP_32K_TIMER) @@ -109,9 +109,6 @@ static void __init omap2_gp_clockevent_init(void) #endif tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); - pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", - CONFIG_OMAP_TICK_GPTIMER, tick_rate); - omap2_gp_timer_irq.dev_id = (void *)gptimer; setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index b16ae761d48..b37fc101e9f 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -11,14 +11,17 @@ choice config ARCH_OMAP1 bool "TI OMAP1" + select COMMON_CLKDEV config ARCH_OMAP2 bool "TI OMAP2" select CPU_V6 + select COMMON_CLKDEV config ARCH_OMAP3 bool "TI OMAP3" select CPU_V7 + select COMMON_CLKDEV endchoice @@ -58,37 +61,6 @@ config OMAP_DEBUG_CLOCKDOMAIN for every clockdomain register write. However, the extra detail costs some memory. -config OMAP_SMARTREFLEX - bool "SmartReflex support" - depends on ARCH_OMAP34XX && TWL4030_CORE - help - Say Y if you want to enable SmartReflex. - - SmartReflex can perform continuous dynamic voltage - scaling around the nominal operating point voltage - according to silicon characteristics and operating - conditions. Enabling SmartReflex reduces power - consumption. - - Please note, that by default SmartReflex is only - initialized. To enable the automatic voltage - compensation for VDD1 and VDD2, user must write 1 to - /sys/power/sr_vddX_autocomp, where X is 1 or 2. - -config OMAP_SMARTREFLEX_TESTING - bool "Smartreflex testing support" - depends on OMAP_SMARTREFLEX - default n - help - Say Y if you want to enable SmartReflex testing with SW hardcoded - NVALUES intead of E-fuse NVALUES set in factory silicon testing. - - In some devices the E-fuse values have not been set, even though - SmartReflex modules are included. Using these hardcoded values set - in software, one can test the SmartReflex features without E-fuse. - - WARNING: Enabling this option may cause your device to hang! - config OMAP_RESET_CLOCKS bool "Reset unused clocks during boot" depends on ARCH_OMAP @@ -208,21 +180,6 @@ config OMAP_32K_TIMER_HZ Kernel internal timer frequency should be a divisor of 32768, such as 64 or 128. -config OMAP_TICK_GPTIMER - int "GPTIMER used for system tick timer" - depends on ARCH_OMAP2 || ARCH_OMAP3 - range 1 12 - default 1 - help - Linux uses one of the twelve on-board OMAP GPTIMER blocks to generate - system tick interrupts. The twelve GPTIMERs have slightly - different powerdomain, source clock, and security properties - (mostly documented in the OMAP3 TRMs) that can affect the selection - of which GPTIMER to use. The historical default is GPTIMER1. - If CONFIG_OMAP_32K_TIMER is selected, Beagle may require GPTIMER12 - due to hardware sensitivity to glitches on the OMAP 32kHz clock - input. - config OMAP_DM_TIMER bool "Use dual-mode timer" depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index bdf2cd444da..2e0614552ac 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -23,8 +23,6 @@ #include #include #include -#include -#include #include @@ -34,183 +32,10 @@ static DEFINE_SPINLOCK(clockfw_lock); static struct clk_functions *arch_clock; -/** - * omap_clk_for_each_child - call callback on each child clock of clk - * @clk: struct clk * to use as the "parent" - * @parent_rate: rate of the parent of @clk to pass along - * @rate_storage: flag indicating whether current or temporary rates are used - * @cb: pointer to a callback function - * - * For each child clock of @clk, call the callback function @cb, passing - * along the contents of @parent_rate and @rate_storage. If the callback - * function returns non-zero, terminate the function and pass along the - * return value. - */ -static int omap_clk_for_each_child(struct clk *clk, unsigned long parent_rate, - u8 rate_storage, - int (*cb)(struct clk *clk, - unsigned long parent_rate, - u8 rate_storage)) -{ - struct clk_child *child; - int ret; - - list_for_each_entry(child, &clk->children, node) { - ret = (*cb)(child->clk, parent_rate, rate_storage); - if (ret) - break; - } - - return ret; -} - -/** - * omap_clk_has_children - does clk @clk have any child clocks? - * @clk: struct clk * to test for child clocks - * - * If clock @clk has any child clocks, return 1; otherwise, return 0. - */ -static int omap_clk_has_children(struct clk *clk) -{ - return (list_empty(&clk->children)) ? 0 : 1; -} - -/** - * _do_propagate_rate - callback function for rate propagation - * @clk: struct clk * to recalc and propagate from - * @parent_rate: rate of the parent of @clk, to use in recalculation - * @rate_storage: flag indicating whether current or temporary rates are used - * - * If @clk has a recalc function, call it. If @clk has any children, - * propagate @clk's rate. Returns 0. - */ -static int _do_propagate_rate(struct clk *clk, unsigned long parent_rate, - u8 rate_storage) -{ - if (clk->recalc) - clk->recalc(clk, parent_rate, rate_storage); - if (omap_clk_has_children(clk)) - propagate_rate(clk, rate_storage); - return 0; -} - -/** - * omap_clk_add_child - add a child clock @clk2 to @clk - * @clk: parent struct clk * - * @clk2: new child struct clk * - * - * Add a child clock @clk2 to the list of children of parent clock - * @clk. Will potentially allocate memory from bootmem or, if - * available, from slab. Must only be called with the clock framework - * spinlock held. No return value. - */ -void omap_clk_add_child(struct clk *clk, struct clk *clk2) -{ - struct clk_child *child; - int reuse = 0; - - if (!clk->children.next) - INIT_LIST_HEAD(&clk->children); - - list_for_each_entry(child, &clk->children, node) { - if (child->flags & CLK_CHILD_DELETED) { - reuse = 1; - child->flags &= ~CLK_CHILD_DELETED; - break; - } - } - - if (!reuse) { - if (slab_is_available()) - child = kmalloc(sizeof(struct clk_child), GFP_ATOMIC); - else - child = alloc_bootmem(sizeof(struct clk_child)); - - if (!child) { - WARN_ON(1); - return; - } - - memset(child, 0, sizeof(struct clk_child)); - - if (slab_is_available()) - child->flags |= CLK_CHILD_SLAB_ALLOC; - } - - child->clk = clk2; - - list_add_tail(&child->node, &clk->children); -} - -/** - * omap_clk_del_child - add a child clock @clk2 to @clk - * @clk: parent struct clk * - * @clk2: former child struct clk * - * - * Remove a child clock @clk2 from the list of children of parent - * clock @clk. Must only be called with the clock framework spinlock - * held. No return value. - */ -void omap_clk_del_child(struct clk *clk, struct clk *clk2) -{ - struct clk_child *child, *tmp; - - /* Loop over all existing clk_childs, when found, deallocate */ - list_for_each_entry_safe(child, tmp, &clk->children, node) { - if (child->clk == clk2) { - list_del(&child->node); - if (child->flags & CLK_CHILD_SLAB_ALLOC) { - kfree(child); - } else { - child->clk = NULL; - child->flags |= CLK_CHILD_DELETED; - } - break; - } - } -} - /*------------------------------------------------------------------------- * Standard clock functions defined in include/linux/clk.h *-------------------------------------------------------------------------*/ -/* - * Returns a clock. Note that we first try to use device id on the bus - * and clock name. If this fails, we try to use clock name only. - */ -struct clk * clk_get(struct device *dev, const char *id) -{ - struct clk *p, *clk = ERR_PTR(-ENOENT); - int idno; - - if (dev == NULL || dev->bus != &platform_bus_type) - idno = -1; - else - idno = to_platform_device(dev)->id; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(p, &clocks, node) { - if (p->id == idno && strcmp(id, p->name) == 0) { - clk = p; - goto found; - } - } - - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0) { - clk = p; - break; - } - } - -found: - mutex_unlock(&clocks_mutex); - - return clk; -} -EXPORT_SYMBOL(clk_get); - int clk_enable(struct clk *clk) { unsigned long flags; @@ -220,13 +45,8 @@ int clk_enable(struct clk *clk) return -EINVAL; spin_lock_irqsave(&clockfw_lock, flags); - if (arch_clock->clk_enable) { + if (arch_clock->clk_enable) ret = arch_clock->clk_enable(clk); - if (ret == 0 && clk->flags & RECALC_ON_ENABLE) - _do_propagate_rate(clk, clk->parent->rate, - CURRENT_RATE); - } - spin_unlock_irqrestore(&clockfw_lock, flags); return ret; @@ -248,12 +68,8 @@ void clk_disable(struct clk *clk) goto out; } - if (arch_clock->clk_disable) { + if (arch_clock->clk_disable) arch_clock->clk_disable(clk); - if (clk->flags & RECALC_ON_ENABLE) - _do_propagate_rate(clk, clk->parent->rate, - CURRENT_RATE); - } out: spin_unlock_irqrestore(&clockfw_lock, flags); @@ -276,11 +92,6 @@ unsigned long clk_get_rate(struct clk *clk) } EXPORT_SYMBOL(clk_get_rate); -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - /*------------------------------------------------------------------------- * Optional clock functions defined in include/linux/clk.h *-------------------------------------------------------------------------*/ @@ -311,14 +122,13 @@ int clk_set_rate(struct clk *clk, unsigned long rate) return ret; spin_lock_irqsave(&clockfw_lock, flags); - - if (arch_clock->clk_set_rate) { + if (arch_clock->clk_set_rate) ret = arch_clock->clk_set_rate(clk, rate); - if (ret == 0) - _do_propagate_rate(clk, clk->parent->rate, - CURRENT_RATE); + if (ret == 0) { + if (clk->recalc) + clk->rate = clk->recalc(clk); + propagate_rate(clk); } - spin_unlock_irqrestore(&clockfw_lock, flags); return ret; @@ -328,25 +138,22 @@ EXPORT_SYMBOL(clk_set_rate); int clk_set_parent(struct clk *clk, struct clk *parent) { unsigned long flags; - struct clk *prev_parent; int ret = -EINVAL; if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) return ret; spin_lock_irqsave(&clockfw_lock, flags); - - if (arch_clock->clk_set_parent) { - prev_parent = clk->parent; - ret = arch_clock->clk_set_parent(clk, parent); + if (clk->usecount == 0) { + if (arch_clock->clk_set_parent) + ret = arch_clock->clk_set_parent(clk, parent); if (ret == 0) { - omap_clk_del_child(prev_parent, clk); - omap_clk_add_child(parent, clk); - _do_propagate_rate(clk, clk->parent->rate, - CURRENT_RATE); + if (clk->recalc) + clk->rate = clk->recalc(clk); + propagate_rate(clk); } - } - + } else + ret = -EBUSY; spin_unlock_irqrestore(&clockfw_lock, flags); return ret; @@ -355,18 +162,7 @@ EXPORT_SYMBOL(clk_set_parent); struct clk *clk_get_parent(struct clk *clk) { - unsigned long flags; - struct clk * ret = NULL; - - if (clk == NULL || IS_ERR(clk)) - return ret; - - spin_lock_irqsave(&clockfw_lock, flags); - if (arch_clock->clk_get_parent) - ret = arch_clock->clk_get_parent(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; + return clk->parent; } EXPORT_SYMBOL(clk_get_parent); @@ -395,32 +191,36 @@ static int __init omap_clk_setup(char *str) __setup("mpurate=", omap_clk_setup); /* Used for clocks that always have same value as the parent clock */ -void followparent_recalc(struct clk *clk, unsigned long new_parent_rate, - u8 rate_storage) +unsigned long followparent_recalc(struct clk *clk) { - if (rate_storage == CURRENT_RATE) - clk->rate = new_parent_rate; - else if (rate_storage == TEMP_RATE) - clk->temp_rate = new_parent_rate; + return clk->parent->rate; } -/* Propagate rate to children */ -void propagate_rate(struct clk *tclk, u8 rate_storage) +void clk_reparent(struct clk *child, struct clk *parent) { - unsigned long parent_rate = 0; + list_del_init(&child->sibling); + if (parent) + list_add(&child->sibling, &parent->children); + child->parent = parent; - if (tclk == NULL || IS_ERR(tclk)) - return; + /* now do the debugfs renaming to reattach the child + to the proper parent */ +} - if (rate_storage == CURRENT_RATE) - parent_rate = tclk->rate; - else if (rate_storage == TEMP_RATE) - parent_rate = tclk->temp_rate; +/* Propagate rate to children */ +void propagate_rate(struct clk * tclk) +{ + struct clk *clkp; - omap_clk_for_each_child(tclk, parent_rate, rate_storage, - _do_propagate_rate); + list_for_each_entry(clkp, &tclk->children, sibling) { + if (clkp->recalc) + clkp->rate = clkp->recalc(clkp); + propagate_rate(clkp); + } } +static LIST_HEAD(root_clks); + /** * recalculate_root_clocks - recalculate and propagate all root clocks * @@ -432,85 +232,56 @@ void recalculate_root_clocks(void) { struct clk *clkp; - list_for_each_entry(clkp, &clocks, node) - if (unlikely(!clkp->parent)) - _do_propagate_rate(clkp, 0, CURRENT_RATE); + list_for_each_entry(clkp, &root_clks, sibling) { + if (clkp->recalc) + clkp->rate = clkp->recalc(clkp); + propagate_rate(clkp); + } } -int clk_register(struct clk *clk) +void clk_init_one(struct clk *clk) { - int ret; + INIT_LIST_HEAD(&clk->children); +} +int clk_register(struct clk *clk) +{ if (clk == NULL || IS_ERR(clk)) return -EINVAL; + /* + * trap out already registered clocks + */ + if (clk->node.next || clk->node.prev) + return 0; + mutex_lock(&clocks_mutex); - if (arch_clock->clk_register) { - ret = arch_clock->clk_register(clk); - if (ret) - goto cr_out; - } - list_add(&clk->node, &clocks); - if (!clk->children.next) - INIT_LIST_HEAD(&clk->children); if (clk->parent) - omap_clk_add_child(clk->parent, clk); + list_add(&clk->sibling, &clk->parent->children); + else + list_add(&clk->sibling, &root_clks); + + list_add(&clk->node, &clocks); if (clk->init) clk->init(clk); - ret = 0; -cr_out: mutex_unlock(&clocks_mutex); - return ret; + return 0; } EXPORT_SYMBOL(clk_register); void clk_unregister(struct clk *clk) { - struct clk_child *child, *tmp; - if (clk == NULL || IS_ERR(clk)) return; mutex_lock(&clocks_mutex); + list_del(&clk->sibling); list_del(&clk->node); - if (clk->parent) - omap_clk_del_child(clk->parent, clk); - list_for_each_entry_safe(child, tmp, &clk->children, node) - if (child->flags & CLK_CHILD_SLAB_ALLOC) - kfree(child); mutex_unlock(&clocks_mutex); } EXPORT_SYMBOL(clk_unregister); -void clk_deny_idle(struct clk *clk) -{ - unsigned long flags; - - if (clk == NULL || IS_ERR(clk)) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - if (arch_clock->clk_deny_idle) - arch_clock->clk_deny_idle(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); -} -EXPORT_SYMBOL(clk_deny_idle); - -void clk_allow_idle(struct clk *clk) -{ - unsigned long flags; - - if (clk == NULL || IS_ERR(clk)) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - if (arch_clock->clk_allow_idle) - arch_clock->clk_allow_idle(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); -} -EXPORT_SYMBOL(clk_allow_idle); - void clk_enable_init_clocks(void) { struct clk *clkp; @@ -522,6 +293,23 @@ void clk_enable_init_clocks(void) } EXPORT_SYMBOL(clk_enable_init_clocks); +/* + * Low level helpers + */ +static int clkll_enable_null(struct clk *clk) +{ + return 0; +} + +static void clkll_disable_null(struct clk *clk) +{ +} + +const struct clkops clkops_null = { + .enable = clkll_enable_null, + .disable = clkll_disable_null, +}; + #ifdef CONFIG_CPU_FREQ void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) { @@ -547,11 +335,10 @@ static int __init clk_disable_unused(void) unsigned long flags; list_for_each_entry(ck, &clocks, node) { - if (ck->usecount > 0 || - (ck->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))) + if (ck->ops == &clkops_null) continue; - if (cpu_class_is_omap1() && ck->enable_reg == 0) + if (ck->usecount > 0 || ck->enable_reg == 0) continue; spin_lock_irqsave(&clockfw_lock, flags); diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c index f412c19c3c5..843e8af6406 100644 --- a/arch/arm/plat-omap/cpu-omap.c +++ b/arch/arm/plat-omap/cpu-omap.c @@ -23,8 +23,8 @@ #include #include -#include #include +#include #define VERY_HI_RATE 900000000 diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 6b742a8ee4e..87fb7ff4179 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -14,19 +14,20 @@ #include #include #include -#include #include #include #include #include +#include #include #include #include #include -#include +#include #include +#include #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) diff --git a/arch/arm/plat-omap/include/mach/board-3430sdp.h b/arch/arm/plat-omap/include/mach/board-3430sdp.h deleted file mode 100644 index ce935cf2247..00000000000 --- a/arch/arm/plat-omap/include/mach/board-3430sdp.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/board-3430sdp.h - * - * Hardware definitions for TI OMAP3430 SDP board. - * - * Initial creation by Syed Mohammed Khasim - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP_3430SDP_H -#define __ASM_ARCH_OMAP_3430SDP_H - -extern void sdp3430_usb_init(void); -extern void sdp3430_flash_init(void); -extern void twl4030_bci_battery_init(void); - -/* NAND */ -/* IMPORTANT NOTE ON MAPPING - * 3430SDP - 34XX - * ---------- - * NOR always on 0x04000000 for SDPV1 - * NOR always on 0x10000000 for SDPV2 - * MPDB always on 0x08000000 - * NAND always on 0x0C000000 - * OneNand Mapped to 0x20000000 - * Boot Mode(NAND/NOR). The other on CS1 - */ -#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (64 Meg aligned) */ -#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (256 Meg aligned) */ -#define DEBUG_BASE 0x08000000 /* debug board */ -#define NAND_BASE 0x0C000000 /* NAND flash */ -#define ONENAND_MAP 0x20000000 /* OneNand flash */ - -/* various memory sizes */ -#define FLASH_SIZE_SDPV1 SZ_64M -#define FLASH_SIZE_SDPV2 SZ_128M - -#endif /* __ASM_ARCH_OMAP_3430SDP_H */ - diff --git a/arch/arm/plat-omap/include/mach/board-omap2evm.h b/arch/arm/plat-omap/include/mach/board-omap2evm.h deleted file mode 100644 index c6ba4282e42..00000000000 --- a/arch/arm/plat-omap/include/mach/board-omap2evm.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/board-omap2evm.h - * - * Hardware definitions for Mistral's OMAP2EVM board. - * - * Based on board-2430sdp.h - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP2_EVM_H -#define __ASM_ARCH_OMAP2_EVM_H - -/* Placeholder for OMAP2EVM specific defines */ -#define OMAP2EVM_ETHR_START 0x2c000000 -#define OMAP2EVM_ETHR_SIZE 1024 -#define OMAP2EVM_ETHR_GPIO_IRQ 149 -#define OMAP2_EVM_TS_GPIO 85 - -#endif /* __ASM_ARCH_OMAP2_EVM_H */ diff --git a/arch/arm/plat-omap/include/mach/board-omap3beagle.h b/arch/arm/plat-omap/include/mach/board-omap3beagle.h deleted file mode 100644 index 3080d52d877..00000000000 --- a/arch/arm/plat-omap/include/mach/board-omap3beagle.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/board-omap3beagle.h - * - * Hardware definitions for TI OMAP3 BEAGLE. - * - * Initial creation by Syed Mohammed Khasim - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP3_BEAGLE_H -#define __ASM_ARCH_OMAP3_BEAGLE_H - -#endif /* __ASM_ARCH_OMAP3_BEAGLE_H */ - diff --git a/arch/arm/plat-omap/include/mach/board-omap3evm.h b/arch/arm/plat-omap/include/mach/board-omap3evm.h deleted file mode 100644 index 7a540e9e1af..00000000000 --- a/arch/arm/plat-omap/include/mach/board-omap3evm.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/board-omap3evm.h - * - * Hardware definitions for TI OMAP3 EVM. - * - * Initial creation by Syed Mohammed Khasim - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP3_EVM_H -#define __ASM_ARCH_OMAP3_EVM_H - -extern void omap3evm_flash_init(void); - -#define OMAP3_EVM_TS_GPIO 175 - -#define ONENAND_MAP 0x20000000 - -#define OMAP3EVM_ETHR_START 0x2c000000 -#define OMAP3EVM_ETHR_SIZE 1024 -#define OMAP3EVM_ETHR_GPIO_IRQ 176 -#define OMAP3EVM_SMC911X_CS 5 - -#endif /* __ASM_ARCH_OMAP3_EVM_H */ - diff --git a/arch/arm/plat-omap/include/mach/board-voiceblue.h b/arch/arm/plat-omap/include/mach/board-voiceblue.h index ed6d346ee12..27916b210f5 100644 --- a/arch/arm/plat-omap/include/mach/board-voiceblue.h +++ b/arch/arm/plat-omap/include/mach/board-voiceblue.h @@ -14,7 +14,6 @@ extern void voiceblue_wdt_enable(void); extern void voiceblue_wdt_disable(void); extern void voiceblue_wdt_ping(void); -extern void voiceblue_reset(void); #endif /* __ASM_ARCH_VOICEBLUE_H */ diff --git a/arch/arm/plat-omap/include/mach/clkdev.h b/arch/arm/plat-omap/include/mach/clkdev.h new file mode 100644 index 00000000000..730c49d1ebd --- /dev/null +++ b/arch/arm/plat-omap/include/mach/clkdev.h @@ -0,0 +1,13 @@ +#ifndef __MACH_CLKDEV_H +#define __MACH_CLKDEV_H + +static inline int __clk_get(struct clk *clk) +{ + return 1; +} + +static inline void __clk_put(struct clk *clk) +{ +} + +#endif diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index db57b71a67b..073a2c5569f 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -17,6 +17,11 @@ struct module; struct clk; struct clockdomain; +struct clkops { + int (*enable)(struct clk *); + void (*disable)(struct clk *); +}; + #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) struct clksel_rate { @@ -31,80 +36,61 @@ struct clksel { }; struct dpll_data { + void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; - unsigned long last_rounded_rate; - unsigned int rate_tolerance; - u32 max_tolerance; - struct clk *bypass_clk; + struct clk *clk_bypass; + struct clk *clk_ref; + void __iomem *control_reg; u32 enable_mask; - u16 mult_div1_reg; - u16 control_reg; - u16 max_multiplier; + unsigned int rate_tolerance; + unsigned long last_rounded_rate; u16 last_rounded_m; u8 last_rounded_n; u8 min_divider; u8 max_divider; + u32 max_tolerance; + u16 max_multiplier; # if defined(CONFIG_ARCH_OMAP3) u8 modes; + void __iomem *autoidle_reg; + void __iomem *idlest_reg; + u32 autoidle_mask; + u32 freqsel_mask; + u32 idlest_mask; u8 auto_recal_bit; u8 recal_en_bit; u8 recal_st_bit; - u16 autoidle_reg; - u16 idlest_reg; - u32 autoidle_mask; - u32 idlest_mask; - u32 freqsel_mask; # endif }; #endif -/** - * struct clk_child - used to track the children of a clock - * @clk: child struct clk * - * @node: list_head - * @flags: is this entry allocated in bootmem or slab? is it deleted? - * - * One struct clk_child is allocated for each child clock @clk of a - * parent clock. @flags values are listed below and start with CLK_CHILD_*. - */ -struct clk_child { - struct clk *clk; - struct list_head node; - u8 flags; -}; - struct clk { struct list_head node; + const struct clkops *ops; const char *name; int id; struct clk *parent; - unsigned long rate; - unsigned long temp_rate; struct list_head children; + struct list_head sibling; /* node for children */ + unsigned long rate; __u32 flags; - u32 enable_reg; - void (*recalc)(struct clk *, unsigned long, u8); + void __iomem *enable_reg; + unsigned long (*recalc)(struct clk *); int (*set_rate)(struct clk *, unsigned long); long (*round_rate)(struct clk *, unsigned long); void (*init)(struct clk *); - int (*enable)(struct clk *); - void (*disable)(struct clk *); __u8 enable_bit; __s8 usecount; - u8 idlest_bit; #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) u8 fixed_div; + void __iomem *clksel_reg; u32 clksel_mask; const struct clksel *clksel; struct dpll_data *dpll_data; - union { - const char *name; - struct clockdomain *ptr; - } clkdm; - u16 clksel_reg; - s16 prcm_mod; + const char *clkdm_name; + struct clockdomain *clkdm; #else __u8 rate_offset; __u8 src_offset; @@ -117,13 +103,11 @@ struct clk { struct cpufreq_frequency_table; struct clk_functions { - int (*clk_register)(struct clk *clk); int (*clk_enable)(struct clk *clk); void (*clk_disable)(struct clk *clk); long (*clk_round_rate)(struct clk *clk, unsigned long rate); int (*clk_set_rate)(struct clk *clk, unsigned long rate); int (*clk_set_parent)(struct clk *clk, struct clk *parent); - struct clk * (*clk_get_parent)(struct clk *clk); void (*clk_allow_idle)(struct clk *clk); void (*clk_deny_idle)(struct clk *clk); void (*clk_disable_unused)(struct clk *clk); @@ -135,70 +119,41 @@ struct clk_functions { extern unsigned int mpurate; extern int clk_init(struct clk_functions *custom_clocks); +extern void clk_init_one(struct clk *clk); extern int clk_register(struct clk *clk); +extern void clk_reparent(struct clk *child, struct clk *parent); extern void clk_unregister(struct clk *clk); -extern void propagate_rate(struct clk *clk, u8 rate_storage); +extern void propagate_rate(struct clk *clk); extern void recalculate_root_clocks(void); -extern void followparent_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage); -extern void clk_allow_idle(struct clk *clk); -extern void clk_deny_idle(struct clk *clk); +extern unsigned long followparent_recalc(struct clk *clk); extern void clk_enable_init_clocks(void); #ifdef CONFIG_CPU_FREQ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); #endif -void omap_clk_add_child(struct clk *clk, struct clk *clk2); -void omap_clk_del_child(struct clk *clk, struct clk *clk2); + +extern const struct clkops clkops_null; /* Clock flags */ -#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ -/* bits 1-3 are currently free */ -#define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */ +/* bit 0 is free */ +#define RATE_FIXED (1 << 1) /* Fixed clock rate */ +/* bits 2-4 are free */ #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ -/* bit 6 is currently free */ #define CLOCK_IDLE_CONTROL (1 << 7) #define CLOCK_NO_IDLE_PARENT (1 << 8) #define DELAYED_APP (1 << 9) /* Delay application of clock */ -/* bit 10 is currently free */ +#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ -#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ -#define WAIT_READY (1 << 13) /* wait for dev to leave idle */ -#define RECALC_ON_ENABLE (1 << 14) /* recalc/prop on ena/disa */ -/* bits 15-20 are currently free */ -#define CLOCK_IN_OMAP310 (1 << 21) -#define CLOCK_IN_OMAP730 (1 << 22) -#define CLOCK_IN_OMAP1510 (1 << 23) -#define CLOCK_IN_OMAP16XX (1 << 24) -#define CLOCK_IN_OMAP242X (1 << 25) -#define CLOCK_IN_OMAP243X (1 << 26) -#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */ -#define PARENT_CONTROLS_CLOCK (1 << 28) -#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */ -#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2+ clocks only */ +#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ +/* bits 13-31 are currently free */ /* Clksel_rate flags */ #define DEFAULT_RATE (1 << 0) #define RATE_IN_242X (1 << 1) #define RATE_IN_243X (1 << 2) #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ -#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2+ rates only */ +#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) -/* rate_storage parameter flags */ -#define CURRENT_RATE 0 -#define TEMP_RATE 1 - -/* clk_child flags */ -#define CLK_CHILD_SLAB_ALLOC (1 << 0) /* if !set, bootmem was used */ -#define CLK_CHILD_DELETED (1 << 1) /* can be reused */ - -/* - * clk.prcm_mod flags (possible since only the top byte in clk.prcm_mod - * is significant) - */ -#define PRCM_MOD_ADDR_MASK 0xff00 -#define CLK_REG_IN_PRM (1 << 0) -#define CLK_REG_IN_SCM (1 << 1) #endif diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h index 8c1b9655b8b..0ecf36deb17 100644 --- a/arch/arm/plat-omap/include/mach/common.h +++ b/arch/arm/plat-omap/include/mach/common.h @@ -33,6 +33,8 @@ struct sys_timer; extern void omap_map_common_io(void); extern struct sys_timer omap_timer; +extern void omap_serial_init(void); +extern void omap_serial_enable_clocks(int enable); #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) extern int omap_register_i2c_bus(int bus_id, u32 clkrate, struct i2c_board_info const *info, @@ -66,10 +68,5 @@ void omap2_set_globals_tap(struct omap_globals *); void omap2_set_globals_sdrc(struct omap_globals *); void omap2_set_globals_control(struct omap_globals *); void omap2_set_globals_prcm(struct omap_globals *); -#ifdef CONFIG_ARCH_OMAP24XX -void omap2_set_globals_clock24xx(struct omap_globals *); -#else -#define omap2_set_globals_clock24xx(x) do { } while (0) -#endif #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h index df7cb4b29e8..269147f3836 100644 --- a/arch/arm/plat-omap/include/mach/control.h +++ b/arch/arm/plat-omap/include/mach/control.h @@ -139,15 +139,6 @@ #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) -#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) -#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) -#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) -#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) -#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) -#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) -#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) -#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) -#define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0) @@ -186,16 +177,6 @@ #define OMAP2_SYSBOOT_1_MASK (1 << 1) #define OMAP2_SYSBOOT_0_MASK (1 << 0) -/* CONTROL_FUSE_SR bits */ -#define OMAP343X_SR2_SENNENABLE_MASK (0x3 << 10) -#define OMAP343X_SR2_SENNENABLE_SHIFT 10 -#define OMAP343X_SR2_SENPENABLE_MASK (0x3 << 8) -#define OMAP343X_SR2_SENPENABLE_SHIFT 8 -#define OMAP343X_SR1_SENNENABLE_MASK (0x3 << 2) -#define OMAP343X_SR1_SENNENABLE_SHIFT 2 -#define OMAP343X_SR1_SENPENABLE_MASK (0x3 << 0) -#define OMAP343X_SR1_SENPENABLE_SHIFT 0 - /* CONTROL_PBIAS_LITE bits */ #define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) #define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) @@ -208,19 +189,6 @@ #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) #define OMAP2_PBIASLITEVMODE0 (1 << 0) -/* CONTROL_PADCONF_X bits */ -#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) -#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) - -/* CONTROL_IVA2_BOOTMOD bits */ -#define OMAP3_IVA2_BOOTMOD_SHIFT 0 -#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) -#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) - -#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) -#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) -#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C - #ifndef __ASSEMBLY__ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) extern void __iomem *omap_ctrl_base_get(void); diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h index 44a0dde6bf2..3dc423ed3e8 100644 --- a/arch/arm/plat-omap/include/mach/hardware.h +++ b/arch/arm/plat-omap/include/mach/hardware.h @@ -286,46 +286,4 @@ #include "omap24xx.h" #include "omap34xx.h" -#ifndef __ASSEMBLER__ - -/* - * --------------------------------------------------------------------------- - * Board specific defines - * --------------------------------------------------------------------------- - */ - -#if defined(CONFIG_MACH_NOKIA_N800) || defined(CONFIG_MACH_NOKIA770) -#include "board-nokia.h" -#endif - -#ifdef CONFIG_MACH_NOKIA_RX51 -#include "board-rx51.h" -#endif - -#ifdef CONFIG_MACH_OMAP2EVM -#include "board-omap2evm.h" -#endif - -#ifdef CONFIG_MACH_OMAP_3430SDP -#include "board-3430sdp.h" -#endif - -#ifdef CONFIG_MACH_OMAP3EVM -#include "board-omap3evm.h" -#endif - -#ifdef CONFIG_MACH_OMAP3_BEAGLE -#include "board-omap3beagle.h" -#endif - -#ifdef CONFIG_MACH_VOICEBLUE -#include "board-voiceblue.h" -#endif - -#ifdef CONFIG_MACH_SX1 -#include "board-sx1.h" -#endif - -#endif /* !__ASSEMBLER__ */ - #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h index ec61b89cf1f..bb154ea7676 100644 --- a/arch/arm/plat-omap/include/mach/mcbsp.h +++ b/arch/arm/plat-omap/include/mach/mcbsp.h @@ -90,8 +90,6 @@ /* Dummy defines, these are not available on omap1 */ #define OMAP_MCBSP_REG_XCCR 0x00 #define OMAP_MCBSP_REG_RCCR 0x00 -#define OMAP_MCBSP_REG_SYSCON 0x00 -#define OMAP_MCBSP_REG_WAKEUPEN 0x00 #define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) #define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) @@ -136,7 +134,6 @@ #define OMAP_MCBSP_REG_XCERG 0x74 #define OMAP_MCBSP_REG_XCERH 0x78 #define OMAP_MCBSP_REG_SYSCON 0x8C -#define OMAP_MCBSP_REG_WAKEUPEN 0xA8 #define OMAP_MCBSP_REG_XCCR 0xAC #define OMAP_MCBSP_REG_RCCR 0xB0 @@ -252,25 +249,8 @@ #define RDISABLE 0x0001 /********************** McBSP SYSCONFIG bit definitions ********************/ -#define CLOCKACTIVITY(value) ((value)<<8) -#define SIDLEMODE(value) ((value)<<3) -#define ENAWAKEUP 0x0004 #define SOFTRST 0x0002 -/********************** McBSP WAKEUPEN bit definitions *********************/ -#define XEMPTYEOFEN 0x4000 -#define XRDYEN 0x0400 -#define XEOFEN 0x0200 -#define XFSXEN 0x0100 -#define XSYNCERREN 0x0080 -#define RRDYEN 0x0008 -#define REOFEN 0x0004 -#define RFSREN 0x0002 -#define RSYNCERREN 0x0001 -#define WAKEUPEN_ALL (XEMPTYEOFEN | XRDYEN | XEOFEN | XFSXEN | \ - XSYNCERREN | RRDYEN | REOFEN | RFSREN | \ - RSYNCERREN) - /* we don't do multichannel for now */ struct omap_mcbsp_reg_cfg { u16 spcr2; @@ -364,8 +344,6 @@ struct omap_mcbsp_platform_data { u8 dma_rx_sync, dma_tx_sync; u16 rx_irq, tx_irq; struct omap_mcbsp_ops *ops; - char const **clk_names; - int num_clks; }; struct omap_mcbsp { @@ -397,8 +375,8 @@ struct omap_mcbsp { /* Protect the field .free, while checking if the mcbsp is in use */ spinlock_t lock; struct omap_mcbsp_platform_data *pdata; - struct clk **clks; - int num_clks; + struct clk *iclk; + struct clk *fclk; }; extern struct omap_mcbsp **mcbsp_ptr; extern int omap_mcbsp_count; diff --git a/arch/arm/plat-omap/include/mach/omap-alsa.h b/arch/arm/plat-omap/include/mach/omap-alsa.h index b0341e7a0cf..bdf30a0f87f 100644 --- a/arch/arm/plat-omap/include/mach/omap-alsa.h +++ b/arch/arm/plat-omap/include/mach/omap-alsa.h @@ -45,33 +45,6 @@ #include #include #include -/* - * Debug functions - */ -#undef DEBUG -/* #define DEBUG */ - -#define ERR(ARGS...) \ - do { \ - printk(KERN_ERR "{%s}-ERROR: ", __func__); \ - printk(ARGS); \ - } while (0) - -#ifdef DEBUG -#define DPRINTK(ARGS...) \ - do { \ - printk(KERN_INFO "<%s>: ", __func__); \ - printk(ARGS); \ - } while (0) -#define ADEBUG() printk("XXX Alsa debug f:%s, l:%d\n", __func__, __LINE__) -#define FN_IN printk(KERN_INFO "[%s]: start\n", __func__) -#define FN_OUT(n) printk(KERN_INFO "[%s]: end(%u)\n", __func__, n) -#else -#define DPRINTK(ARGS...) /* nop */ -#define ADEBUG() /* nop */ -#define FN_IN /* nop */ -#define FN_OUT(n) /* nop */ -#endif #define DMA_BUF_SIZE (1024 * 8) @@ -89,12 +62,12 @@ struct audio_stream { char dma_q_count; /* DMA Channel Q Count */ int active:1; /* we are using this stream for transfer now */ int period; /* current transfer period */ - int periods; /* current registered periods in DMA engine */ + int periods; /* current count of periods registerd in the DMA engine */ spinlock_t dma_lock; /* for locking in DMA operations */ struct snd_pcm_substream *stream; /* the pcm stream */ unsigned linked:1; /* dma channels linked */ - int offset; /* start position of last period in alsa buf */ - int (*hw_start)(void); /* interface to start HW interface, (McBSP) */ + int offset; /* store start position of the last period in the alsa buffer */ + int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */ int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */ }; @@ -135,8 +108,7 @@ void snd_omap_suspend_mixer(void); void snd_omap_resume_mixer(void); #endif -int snd_omap_alsa_post_probe(struct platform_device *pdev, - struct omap_alsa_codec_config *config); +int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config); int snd_omap_alsa_remove(struct platform_device *pdev); #ifdef CONFIG_PM int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state); diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/mach/omap34xx.h index 3bfbdf7ad18..ab640151d3e 100644 --- a/arch/arm/plat-omap/include/mach/omap34xx.h +++ b/arch/arm/plat-omap/include/mach/omap34xx.h @@ -80,12 +80,9 @@ #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) #define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000) #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) -#define OMAP34XX_SR1_BASE 0x480C9000 -#define OMAP34XX_SR2_BASE 0x480CB000 #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) - #if defined(CONFIG_ARCH_OMAP3430) #define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h index b226bdf4573..7b74d1255e0 100644 --- a/arch/arm/plat-omap/include/mach/omapfb.h +++ b/arch/arm/plat-omap/include/mach/omapfb.h @@ -276,8 +276,8 @@ typedef int (*omapfb_notifier_callback_t)(struct notifier_block *, void *fbi); struct omapfb_mem_region { - u32 paddr; - void __iomem *vaddr; + dma_addr_t paddr; + void *vaddr; unsigned long size; u8 type; /* OMAPFB_PLANE_MEM_* */ unsigned alloc:1; /* allocated by the driver */ diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h index faf5b48c61d..ce6ee792753 100644 --- a/arch/arm/plat-omap/include/mach/pm.h +++ b/arch/arm/plat-omap/include/mach/pm.h @@ -107,8 +107,7 @@ #if !defined(CONFIG_ARCH_OMAP730) && \ !defined(CONFIG_ARCH_OMAP15XX) && \ !defined(CONFIG_ARCH_OMAP16XX) && \ - !defined(CONFIG_ARCH_OMAP24XX) && \ - !defined(CONFIG_ARCH_OMAP34XX) + !defined(CONFIG_ARCH_OMAP24XX) #warning "Power management for this processor not implemented yet" #endif @@ -116,38 +115,16 @@ #include -extern struct kset power_subsys; - extern void prevent_idle_sleep(void); extern void allow_idle_sleep(void); -/** - * clk_deny_idle - Prevents the clock from being idled during MPU idle - * @clk: clock signal handle - */ -void clk_deny_idle(struct clk *clk); - -/** - * clk_allow_idle - Counters previous clk_deny_idle - * @clk: clock signal handle - */ -void clk_allow_idle(struct clk *clk); - extern void omap_pm_idle(void); extern void omap_pm_suspend(void); -#ifdef CONFIG_PM -extern void omap2_block_sleep(void); -extern void omap2_allow_sleep(void); -#else -static inline void omap2_block_sleep(void) { } -static inline void omap2_allow_sleep(void) { } -#endif extern void omap730_cpu_suspend(unsigned short, unsigned short); extern void omap1510_cpu_suspend(unsigned short, unsigned short); extern void omap1610_cpu_suspend(unsigned short, unsigned short); extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl, void __iomem *sdrc_power); -extern void omap34xx_cpu_suspend(u32 *addr, int save_state); extern void omap730_idle_loop_suspend(void); extern void omap1510_idle_loop_suspend(void); extern void omap1610_idle_loop_suspend(void); @@ -157,12 +134,10 @@ extern unsigned int omap730_cpu_suspend_sz; extern unsigned int omap1510_cpu_suspend_sz; extern unsigned int omap1610_cpu_suspend_sz; extern unsigned int omap24xx_cpu_suspend_sz; -extern unsigned int omap34xx_cpu_suspend_sz; extern unsigned int omap730_idle_loop_suspend_sz; extern unsigned int omap1510_idle_loop_suspend_sz; extern unsigned int omap1610_idle_loop_suspend_sz; extern unsigned int omap24xx_idle_loop_suspend_sz; -extern unsigned int omap34xx_suspend_sz; #ifdef CONFIG_OMAP_SERIAL_WAKE extern void omap_serial_wake_trigger(int enable); @@ -195,6 +170,10 @@ extern void omap_serial_wake_trigger(int enable); #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x)) #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] +#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x +#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] +#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] + /* * List of global OMAP registers to preserve. * More ones like CP and general purpose register values are preserved @@ -304,5 +283,63 @@ enum mpui1610_save_state { #endif }; +enum omap24xx_save_state { + OMAP24XX_SLEEP_SAVE_START = 0, + OMAP24XX_SLEEP_SAVE_INTC_MIR0, + OMAP24XX_SLEEP_SAVE_INTC_MIR1, + OMAP24XX_SLEEP_SAVE_INTC_MIR2, + + OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU, + OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE, + OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX, + OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP, + OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM, + + OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU, + OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE, + OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX, + OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP, + OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM, + + OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE, + OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE, + OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE, + OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE, + OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX, + OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP, + OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN, + OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP, + OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM, + + OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE, + OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE, + OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE, + OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE, + OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP, + OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL, + OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP, + OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM, + + OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE, + OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE, + OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE, + OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE, + OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE, + OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE, + OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1, + OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1, + OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1, + OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1, + OMAP24XX_SLEEP_SAVE_GPIO3_OE, + OMAP24XX_SLEEP_SAVE_GPIO4_OE, + OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT, + OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT, + OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2, + OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX, + OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX, + OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0, + OMAP24XX_SLEEP_SAVE_SIZE +}; + #endif /* ASSEMBLER */ #endif /* __ASM_ARCH_OMAP_PM_H */ diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/mach/prcm.h index 80dddcb970c..24ac3c71591 100644 --- a/arch/arm/plat-omap/include/mach/prcm.h +++ b/arch/arm/plat-omap/include/mach/prcm.h @@ -26,10 +26,6 @@ u32 omap_prcm_get_reset_sources(void); void omap_prcm_arch_reset(char mode); -void cm_write_mod_reg(u32 val, s16 module, u16 idx); -u32 cm_read_mod_reg(s16 module, u16 idx); -u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); - #endif diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h index c66c8388790..adc73522491 100644 --- a/arch/arm/plat-omap/include/mach/sdrc.h +++ b/arch/arm/plat-omap/include/mach/sdrc.h @@ -21,24 +21,15 @@ /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ #define SDRC_SYSCONFIG 0x010 -#define SDRC_CS_CFG 0x040 -#define SDRC_SHARING 0x044 -#define SDRC_ERR_TYPE 0x04C #define SDRC_DLLA_CTRL 0x060 #define SDRC_DLLA_STATUS 0x064 #define SDRC_DLLB_CTRL 0x068 #define SDRC_DLLB_STATUS 0x06C #define SDRC_POWER 0x070 -#define SDRC_MCFG_0 0x080 #define SDRC_MR_0 0x084 #define SDRC_ACTIM_CTRL_A_0 0x09c #define SDRC_ACTIM_CTRL_B_0 0x0a0 #define SDRC_RFR_CTRL_0 0x0a4 -#define SDRC_MCFG_1 0x0B0 -#define SDRC_MR_1 0x0B4 -#define SDRC_ACTIM_CTRL_A_1 0x0C4 -#define SDRC_ACTIM_CTRL_B_1 0x0C8 -#define SDRC_RFR_CTRL_1 0x0D4 /* * These values represent the number of memory clock cycles between @@ -75,9 +66,12 @@ * SMS register access */ -#define OMAP242X_SMS_REGADDR(reg) IO_ADDRESS(OMAP2420_SMS_BASE + reg) -#define OMAP243X_SMS_REGADDR(reg) IO_ADDRESS(OMAP243X_SMS_BASE + reg) -#define OMAP343X_SMS_REGADDR(reg) IO_ADDRESS(OMAP343X_SMS_BASE + reg) +#define OMAP242X_SMS_REGADDR(reg) \ + (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) +#define OMAP243X_SMS_REGADDR(reg) \ + (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) +#define OMAP343X_SMS_REGADDR(reg) \ + (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) /* SMS register offsets - read/write with sms_{read,write}_reg() */ @@ -108,7 +102,7 @@ struct omap_sdrc_params { u32 mr; }; -void __init omap2_sdrc_init(struct omap_sdrc_params *); +void __init omap2_sdrc_init(struct omap_sdrc_params *sp); struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r); #ifdef CONFIG_ARCH_OMAP2 diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h index 8e895858b3e..8a676a04be4 100644 --- a/arch/arm/plat-omap/include/mach/serial.h +++ b/arch/arm/plat-omap/include/mach/serial.h @@ -40,13 +40,4 @@ __ret; \ }) -#ifndef __ASSEMBLER__ -extern void omap_serial_init(void); -extern int omap_uart_can_sleep(void); -extern void omap_uart_check_wakeup(void); -extern void omap_uart_prepare_suspend(void); -extern void omap_uart_prepare_idle(int num); -extern void omap_uart_resume_idle(int num); -#endif - #endif diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h index e9b95637f7f..3c65ad7f9d6 100644 --- a/arch/arm/plat-omap/include/mach/system.h +++ b/arch/arm/plat-omap/include/mach/system.h @@ -13,6 +13,8 @@ #ifndef CONFIG_MACH_VOICEBLUE #define voiceblue_reset() do {} while (0) +#else +extern void voiceblue_reset(void); #endif static inline void arch_idle(void) diff --git a/arch/arm/plat-omap/include/mach/timex.h b/arch/arm/plat-omap/include/mach/timex.h index b3f5ea96e05..6d35767bc48 100644 --- a/arch/arm/plat-omap/include/mach/timex.h +++ b/arch/arm/plat-omap/include/mach/timex.h @@ -38,6 +38,4 @@ #define CLOCK_TICK_RATE (HZ * 100000UL) #endif -extern struct sys_timer omap_timer; - #endif /* __ASM_ARCH_OMAP_TIMEX_H */ diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index feb286cb0e6..0abfbaa5987 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c @@ -1,7 +1,7 @@ /* * OMAP mailbox driver * - * Copyright (C) 2006-2008 Nokia Corporation. All rights reserved. + * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. * * Contact: Hiroshi DOYU * diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index e2e8b76483c..28b0a824b8c 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -214,7 +214,6 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type); int omap_mcbsp_request(unsigned int id) { struct omap_mcbsp *mcbsp; - int i; int err; if (!omap_mcbsp_check_valid_id(id)) { @@ -223,37 +222,22 @@ int omap_mcbsp_request(unsigned int id) } mcbsp = id_to_mcbsp_ptr(id); - if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) - mcbsp->pdata->ops->request(id); - spin_lock(&mcbsp->lock); if (!mcbsp->free) { dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id); spin_unlock(&mcbsp->lock); - return -1; + return -EBUSY; } mcbsp->free = 0; spin_unlock(&mcbsp->lock); - for (i = 0; i < mcbsp->num_clks; i++) - clk_enable(mcbsp->clks[i]); - - /* - * Enable wakup behavior, smart idle and all wakeups - * REVISIT: some wakeups may be unnecessary - */ - if (cpu_is_omap34xx()) { - u16 w; - - w = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON); - w &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); - w |= (ENAWAKEUP | SIDLEMODE(0x02) | CLOCKACTIVITY(0x02)); - OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, w); + if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) + mcbsp->pdata->ops->request(id); - OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, WAKEUPEN_ALL); - } + clk_enable(mcbsp->iclk); + clk_enable(mcbsp->fclk); /* * Make sure that transmitter, receiver and sample-rate generator are @@ -293,7 +277,6 @@ EXPORT_SYMBOL(omap_mcbsp_request); void omap_mcbsp_free(unsigned int id) { struct omap_mcbsp *mcbsp; - int i; if (!omap_mcbsp_check_valid_id(id)) { printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); @@ -301,24 +284,18 @@ void omap_mcbsp_free(unsigned int id) } mcbsp = id_to_mcbsp_ptr(id); - /* - * Disable wakup behavior, smart idle and all wakeups - */ - if (cpu_is_omap34xx()) { - u16 w; + if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) + mcbsp->pdata->ops->free(id); - w = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON); - w &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); - OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, w); + clk_disable(mcbsp->fclk); + clk_disable(mcbsp->iclk); - w = OMAP_MCBSP_READ(mcbsp->io_base, WAKEUPEN); - w &= ~WAKEUPEN_ALL; - OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, w); + if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { + /* Free IRQs */ + free_irq(mcbsp->rx_irq, (void *)mcbsp); + free_irq(mcbsp->tx_irq, (void *)mcbsp); } - if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) - mcbsp->pdata->ops->free(id); - spin_lock(&mcbsp->lock); if (mcbsp->free) { dev_err(mcbsp->dev, "McBSP%d was not reserved\n", @@ -326,20 +303,9 @@ void omap_mcbsp_free(unsigned int id) spin_unlock(&mcbsp->lock); return; } - spin_unlock(&mcbsp->lock); - - for (i = mcbsp->num_clks - 1; i >= 0; i--) - clk_disable(mcbsp->clks[i]); - spin_lock(&mcbsp->lock); mcbsp->free = 1; spin_unlock(&mcbsp->lock); - - if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { - /* Free IRQs */ - free_irq(mcbsp->rx_irq, (void *)mcbsp); - free_irq(mcbsp->tx_irq, (void *)mcbsp); - } } EXPORT_SYMBOL(omap_mcbsp_free); @@ -908,7 +874,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; struct omap_mcbsp *mcbsp; int id = pdev->id - 1; - int i; int ret = 0; if (!pdata) { @@ -931,7 +896,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) ret = -ENOMEM; goto exit; } - mcbsp_ptr[id] = mcbsp; spin_lock_init(&mcbsp->lock); mcbsp->id = id + 1; @@ -953,39 +917,32 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) mcbsp->dma_rx_sync = pdata->dma_rx_sync; mcbsp->dma_tx_sync = pdata->dma_tx_sync; - if (pdata->num_clks) { - mcbsp->num_clks = pdata->num_clks; - mcbsp->clks = kzalloc(mcbsp->num_clks * sizeof(struct clk *), - GFP_KERNEL); - if (!mcbsp->clks) { - ret = -ENOMEM; - goto exit; - } - for (i = 0; i < mcbsp->num_clks; i++) { - mcbsp->clks[i] = clk_get(&pdev->dev, pdata->clk_names[i]); - if (IS_ERR(mcbsp->clks[i])) { - dev_err(&pdev->dev, - "Invalid %s configuration for McBSP%d.\n", - pdata->clk_names[i], mcbsp->id); - ret = PTR_ERR(mcbsp->clks[i]); - goto err_clk; - } - } + mcbsp->iclk = clk_get(&pdev->dev, "ick"); + if (IS_ERR(mcbsp->iclk)) { + ret = PTR_ERR(mcbsp->iclk); + dev_err(&pdev->dev, "unable to get ick: %d\n", ret); + goto err_iclk; + } + mcbsp->fclk = clk_get(&pdev->dev, "fck"); + if (IS_ERR(mcbsp->fclk)) { + ret = PTR_ERR(mcbsp->fclk); + dev_err(&pdev->dev, "unable to get fck: %d\n", ret); + goto err_fclk; } mcbsp->pdata = pdata; mcbsp->dev = &pdev->dev; + mcbsp_ptr[id] = mcbsp; platform_set_drvdata(pdev, mcbsp); return 0; -err_clk: - while (i--) - clk_put(mcbsp->clks[i]); - kfree(mcbsp->clks); +err_fclk: + clk_put(mcbsp->iclk); +err_iclk: iounmap(mcbsp->io_base); err_ioremap: - mcbsp->free = 0; + kfree(mcbsp); exit: return ret; } @@ -993,7 +950,6 @@ exit: static int __devexit omap_mcbsp_remove(struct platform_device *pdev) { struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); - int i; platform_set_drvdata(pdev, NULL); if (mcbsp) { @@ -1002,18 +958,15 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev) mcbsp->pdata->ops->free) mcbsp->pdata->ops->free(mcbsp->id); - for (i = mcbsp->num_clks - 1; i >= 0; i--) { - clk_disable(mcbsp->clks[i]); - clk_put(mcbsp->clks[i]); - } + clk_disable(mcbsp->fclk); + clk_disable(mcbsp->iclk); + clk_put(mcbsp->fclk); + clk_put(mcbsp->iclk); iounmap(mcbsp->io_base); - if (mcbsp->num_clks) { - kfree(mcbsp->clks); - mcbsp->clks = NULL; - mcbsp->num_clks = 0; - } + mcbsp->fclk = NULL; + mcbsp->iclk = NULL; mcbsp->free = 0; mcbsp->dev = NULL; } @@ -1034,4 +987,3 @@ int __init omap_mcbsp_init(void) /* Register the McBSP driver */ return platform_driver_register(&omap_mcbsp_driver); } - diff --git a/drivers/bluetooth/brf6150.c b/drivers/bluetooth/brf6150.c index 2d22aec1a52..211fa5e0c64 100644 --- a/drivers/bluetooth/brf6150.c +++ b/drivers/bluetooth/brf6150.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include -- 2.41.1