From eb589a09a6feab16bdada3fb6c25a571c04b9362 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 2 Aug 2007 12:10:05 -0600 Subject: [PATCH] omap2 clock: fix clksel divisor bug For clksel clocks, omap2_clk_set_rate() incorrectly divides the parent clock's rate by the actual bits of the register field, rather than the translated divisor value. This happens to work for most clksel clocks, since the register bit fields are equal to the divisor values. But for some clocks, such as sys_clkout, the code gets the resulting rate wrong. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index e23ddf5f2e6..94e31a98697 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -819,7 +819,7 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate) reg_val |= (field_val << div_off); cm_write_reg(reg_val, reg); wmb(); - clk->rate = clk->parent->rate / field_val; + clk->rate = clk->parent->rate / new_div; if (clk->flags & DELAYED_APP) { prm_write_reg(OMAP24XX_VALID_CONFIG, -- 2.41.1