From dc9c8e218da823008ce1572998902a4bdf46af37 Mon Sep 17 00:00:00 2001 From: Wei Ni Date: Fri, 26 Sep 2008 13:55:56 +0800 Subject: [PATCH] ALSA: Fix for reading RIRB buffer on NVIDIA aza controller with AMD Phenom cpu When read RIRB buffer immediately after RIRB interrupt received, sometimes the data will be "0x0". If we wait for some time, the data in buffer will be correct. This issue only occurred with AMD Phenom cpu. So we set this "needs_damn_long_delay" flag. Signed-off-by: Wei Ni Signed-off-by: Takashi Iwai Signed-off-by: Jaroslav Kysela --- sound/pci/hda/hda_intel.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 60cc44abf58..9f316c1b279 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -1220,6 +1220,9 @@ static int __devinit azx_codec_create(struct azx *chip, const char *model, if (err < 0) return err; + if (chip->driver_type == AZX_DRIVER_NVIDIA) + chip->bus->needs_damn_long_delay = 1; + codecs = audio_codecs = 0; max_slots = azx_max_codecs[chip->driver_type]; if (!max_slots) -- 2.41.1