From c6051183c597b6a0fa73cdb59aac852c6148c5b6 Mon Sep 17 00:00:00 2001 From: Timo Teras Date: Mon, 9 Oct 2006 18:49:49 +0300 Subject: [PATCH] ARM: OMAP: Proper handling of DMA4_IRQSTATUS_L0 The register bits are reset by writing one. Remove the unneeded reads and fix writes to not clear too many bits. Signed-off-by: Timo Teras Signed-off-by: Juha Yrjola --- arch/arm/plat-omap/dma.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 713401715dc..f9e11275b88 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -557,7 +557,7 @@ int omap_request_dma(int dev_id, const char *dev_name, omap_enable_channel_irq(free_ch); /* Clear the CSR register and IRQ status register */ OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK; - omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0); + omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0); } *dma_ch_out = free_ch; @@ -597,10 +597,7 @@ void omap_free_dma(int lch) /* Clear the CSR register and IRQ status register */ OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; - - val = omap_readl(OMAP_DMA4_IRQSTATUS_L0); - val |= 1 << lch; - omap_writel(val, OMAP_DMA4_IRQSTATUS_L0); + omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0); /* Disable all DMA interrupts for the channel. */ OMAP_DMA_CICR_REG(lch) = 0; @@ -928,7 +925,6 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id, static int omap2_dma_handle_ch(int ch) { u32 status = OMAP_DMA_CSR_REG(ch); - u32 val; if (!status) { if (printk_ratelimit()) @@ -956,11 +952,7 @@ static int omap2_dma_handle_ch(int ch) dma_chan[ch].dev_id); OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK; - - val = omap_readl(OMAP_DMA4_IRQSTATUS_L0); - /* ch in this function is from 0-31 while in register it is 1-32 */ - val = 1 << (ch); - omap_writel(val, OMAP_DMA4_IRQSTATUS_L0); + omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); if (likely(dma_chan[ch].callback != NULL)) dma_chan[ch].callback(ch, status, dma_chan[ch].data); -- 2.41.1