From b54b8db107ab453eeb47287bec5e3088523cc916 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 7 Nov 2005 14:17:33 -0800 Subject: [PATCH] ARM: OMAP: Make 24xx timer check source clock instead of hardcoded value Make 24xx timer check source clock instead of hardcoded value --- arch/arm/mach-omap2/timer-gp.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index dbd867dd35a..1ea91681926 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -20,9 +20,11 @@ #include #include #include +#include #include #include #include +#include #define OMAP2_GP_TIMER1_BASE 0x48028000 #define OMAP2_GP_TIMER2_BASE 0x4802a000 @@ -56,6 +58,7 @@ static inline void timer_write_reg(int nr, unsigned int reg, unsigned int val) __raw_writel(val, timer_base[nr] + reg); } +/* Note that we always enable the clock prescale divider bit */ static inline void omap2_gp_timer_start(int nr, unsigned long load_val) { unsigned int tmp; @@ -87,19 +90,34 @@ static struct irqaction omap2_gp_timer_irq = { .handler = omap2_gp_timer_interrupt, }; -#define MPU_TIMER_TICK_PERIOD (192000 - 1) - static void __init omap2_gp_timer_init(void) { + struct clk * osc_ck; + u32 tick_period = 120000; u32 l; + /* Reset clock and prescale value */ + timer_write_reg(OS_TIMER_NR, GP_TIMER_TCLR, 0); + + osc_ck = clk_get(NULL, "osc_ck"); + if (IS_ERR(osc_ck)) + printk(KERN_ERR "Could not get osc_ck\n"); + else { + clk_use(osc_ck); + tick_period = clk_get_rate(osc_ck) / 100; + clk_put(osc_ck); + } + + tick_period /= 2; /* Minimum prescale divider is 2 */ + tick_period -= 1; + l = timer_read_reg(OS_TIMER_NR, GP_TIMER_TIDR); printk(KERN_INFO "OMAP2 GP timer (HW version %d.%d)\n", (l >> 4) & 0x0f, l & 0x0f); setup_irq(38, &omap2_gp_timer_irq); - omap2_gp_timer_start(OS_TIMER_NR, MPU_TIMER_TICK_PERIOD); + omap2_gp_timer_start(OS_TIMER_NR, tick_period); } struct sys_timer omap_timer = { -- 2.41.1