From a4f77550bcc72e51b3b07dd6e259ee9d4c07cf40 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 2 Aug 2007 12:10:14 -0600 Subject: [PATCH] omap2 clock: vlynq_fck is missing clksel divider code vlynq_fck is a clksel clock. But omap2_clk_set_parent() is missing the code to divide its parent's rate down appropriately when vlynq_fck is set to use a core_ck parent. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index be2f12b1062..f5ea6798740 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -823,7 +823,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset, if (src_clk == &func_96m_ck) val = 0; else if (src_clk == &core_ck) - val = 0x10; + val = 0x10; /* rate needs fixing */ } break; case CM_CORE_SEL2: @@ -934,7 +934,8 @@ static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) clk->parent = new_parent; /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/ - if ((new_parent == &core_ck) && (clk == &dss1_fck)) + if ((new_parent == &core_ck) && + (clk == &dss1_fck || clk == &vlynq_fck)) clk->rate = new_parent->rate / 0x10; else clk->rate = new_parent->rate; -- 2.41.1