From 9edc7c828df5856bb65024bf344e126cd739f80e Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Mon, 12 Nov 2007 03:57:27 -0700 Subject: [PATCH] 3430 clock: revise SmartReflex clocks The two SmartReflex voltage controllers on OMAP3430 have one functional clock each. These clocks appear to be independent of each other. Encode them appropriately, replacing the previous 'sr_alwon_fck' clock. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock34xx.h | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 8fd46d4fb7f..d6dea3978a1 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -2012,11 +2012,23 @@ static struct clk mcbsp4_fck = { /* SR clocks */ -/* REVISIT: dependent on en_sr1 && en_sr2 - use custom enable/disable? */ -static struct clk sr_alwon_fck = { - .name = "sr_alwon_fck", +/* SmartReflex fclk (VDD1) */ +static struct clk sr1_fck = { + .name = "sr1_fck", .parent = &sys_ck, - .flags = CLOCK_IN_OMAP343X, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_SR1_SHIFT, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .recalc = &followparent_recalc, +}; + +/* SmartReflex fclk (VDD2) */ +static struct clk sr2_fck = { + .name = "sr2_fck", + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_SR2_SHIFT, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -2213,7 +2225,8 @@ static struct clk *onchip_34xx_clks[] __initdata = { &mcbsp2_fck, &mcbsp3_fck, &mcbsp4_fck, - &sr_alwon_fck, + &sr1_fck, + &sr2_fck, &sr_l4_ick, &secure_32k_fck, &gpt12_fck, -- 2.41.1