From 9c909ac90902a9c0ecca2bc9ac36289cb84990f5 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 18 Sep 2008 10:30:31 -0600 Subject: [PATCH] OMAP3 clock: DPLLs should enter bypass if new rate is sys_ck This patch causes a DPLL to enter bypass when it is instructed to set its rate to that of its bypass clock. Previously this was only possible after setting the DPLL rate, then disabling and re-enabling it. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock34xx.c | 40 ++++++++++++++++++++++++--------- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 6963f2e17b1..520fc351bb6 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -371,13 +371,17 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) * @clk: struct clk * of DPLL to set * @rate: rounded target rate * - * Program the DPLL with the rounded target rate. Returns -EINVAL upon - * error, or 0 upon success. + * Set the DPLL CLKOUT to the target rate. If the DPLL can enter + * low-power bypass, and the target rate is the bypass source clock + * rate, then configure the DPLL for bypass. Otherwise, round the + * target rate if it hasn't been done already, then program and lock + * the DPLL. Returns -EINVAL upon error, or 0 upon success. */ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) { u16 freqsel; struct dpll_data *dd; + int ret; if (!clk || !rate) return -EINVAL; @@ -389,18 +393,32 @@ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) if (rate == omap2_get_dpll_rate(clk)) return 0; - if (dd->last_rounded_rate != rate) - omap2_dpll_round_rate(clk, rate); + if (dd->bypass_clk->rate == rate && + (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { - if (dd->last_rounded_rate == 0) - return -EINVAL; + pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); + + ret = _omap3_noncore_dpll_bypass(clk); + + } else { + + if (dd->last_rounded_rate != rate) + omap2_dpll_round_rate(clk, rate); - freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); - if (!freqsel) - WARN_ON(1); + if (dd->last_rounded_rate == 0) + return -EINVAL; - omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n, - freqsel); + freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); + if (!freqsel) + WARN_ON(1); + + pr_debug("clock: %s: set rate: locking rate to %lu.\n", + clk->name, rate); + + ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, + dd->last_rounded_n, freqsel); + + } omap3_dpll_recalc(clk); -- 2.41.1