From 8fd7132dce3a3299d032a64e24c3ef96b60c1bd6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 20 Sep 2005 13:02:05 +0300 Subject: [PATCH] ARM: OMAP: Modifiy common clock.h for omap2, add omap1 specific clock.h Modifiy common clock.h for omap2, add omap1 specific clock.h --- arch/arm/mach-omap1/clock.c | 704 +-------------------------- arch/arm/mach-omap1/clock.h | 768 ++++++++++++++++++++++++++++++ arch/arm/plat-omap/clock.c | 4 +- include/asm-arm/arch-omap/clock.h | 110 ++--- 4 files changed, 801 insertions(+), 785 deletions(-) create mode 100644 arch/arm/mach-omap1/clock.h diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index b66a0588201..3e2b546a9ef 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -21,712 +21,10 @@ #include #include -static int omap1_clk_enable(struct clk * clk); -static void omap1_clk_disable(struct clk * clk); -static void omap1_ckctl_recalc(struct clk * clk); -static void omap1_watchdog_recalc(struct clk * clk); -static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); -static int omap1_clk_enable_dsp_domain(struct clk * clk); -static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); -static void omap1_clk_disable_dsp_domain(struct clk * clk); -static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); -static void omap1_uart_recalc(struct clk * clk); -static int omap1_clk_enable_uart_functional(struct clk * clk); -static void omap1_clk_disable_uart_functional(struct clk * clk); -static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); -static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); -static void omap1_init_ext_clk(struct clk * clk); -static int omap1_select_table_rate(struct clk * clk, unsigned long rate); -static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); -static int omap1_clk_use(struct clk *clk); -static void omap1_clk_unuse(struct clk *clk); - -struct mpu_rate { - unsigned long rate; - unsigned long xtal; - unsigned long pll_rate; - __u16 ckctl_val; - __u16 dpllctl_val; -}; - -struct uart_clk { - struct clk clk; - unsigned long sysc_addr; -}; +#include "clock.h" -/* Provide a method for preventing idling some ARM IDLECT clocks */ -struct arm_idlect1_clk { - struct clk clk; - unsigned long no_idle_count; - __u8 idlect_shift; -}; __u32 arm_idlect1_mask; -/* Omap1 MPU rate table */ -static struct mpu_rate rate_table[] = { - /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL - * NOTE: Comment order here is different from bits in CKCTL value: - * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv - */ -#if defined(CONFIG_OMAP_ARM_216MHZ) - { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_195MHZ) - { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_192MHZ) - { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ - { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ - { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ - { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ - { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_182MHZ) - { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_168MHZ) - { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_150MHZ) - { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ -#endif -#if defined(CONFIG_OMAP_ARM_120MHZ) - { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ -#endif -#if defined(CONFIG_OMAP_ARM_96MHZ) - { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ -#endif -#if defined(CONFIG_OMAP_ARM_60MHZ) - { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ -#endif -#if defined(CONFIG_OMAP_ARM_30MHZ) - { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ -#endif - { 0, 0, 0, 0, 0 }, -}; - -/*------------------------------------------------------------------------- - * Omap1 clocks - *-------------------------------------------------------------------------*/ - -static struct clk ck_ref = { - .name = "ck_ref", - .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - ALWAYS_ENABLED, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk ck_dpll1 = { - .name = "ck_dpll1", - .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - RATE_PROPAGATES | ALWAYS_ENABLED, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct arm_idlect1_clk ck_dpll1out = { - .clk = { - .name = "ck_dpll1out", - .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL, - .enable_reg = ARM_IDLECT2, - .enable_bit = EN_CKOUT_ARM, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, - }, - .idlect_shift = 12, -}; - -static struct clk arm_ck = { - .name = "arm_ck", - .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED, - .rate_offset = CKCTL_ARMDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct arm_idlect1_clk armper_ck = { - .clk = { - .name = "armper_ck", - .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - RATE_CKCTL | CLOCK_IDLE_CONTROL, - .enable_reg = ARM_IDLECT2, - .enable_bit = EN_PERCK, - .rate_offset = CKCTL_PERDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, - }, - .idlect_shift = 2, -}; - -static struct clk arm_gpio_ck = { - .name = "arm_gpio_ck", - .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510, - .enable_reg = ARM_IDLECT2, - .enable_bit = EN_GPIOCK, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct arm_idlect1_clk armxor_ck = { - .clk = { - .name = "armxor_ck", - .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IDLE_CONTROL, - .enable_reg = ARM_IDLECT2, - .enable_bit = EN_XORPCK, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, - }, - .idlect_shift = 1, -}; - -static struct arm_idlect1_clk armtim_ck = { - .clk = { - .name = "armtim_ck", - .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IDLE_CONTROL, - .enable_reg = ARM_IDLECT2, - .enable_bit = EN_TIMCK, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, - }, - .idlect_shift = 9, -}; - -static struct arm_idlect1_clk armwdt_ck = { - .clk = { - .name = "armwdt_ck", - .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IDLE_CONTROL, - .enable_reg = ARM_IDLECT2, - .enable_bit = EN_WDTCK, - .recalc = &omap1_watchdog_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, - }, - .idlect_shift = 0, -}; - -static struct clk arminth_ck16xx = { - .name = "arminth_ck", - .parent = &arm_ck, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, - .recalc = &followparent_recalc, - /* Note: On 16xx the frequency can be divided by 2 by programming - * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 - * - * 1510 version is in TC clocks. - */ - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk dsp_ck = { - .name = "dsp_ck", - .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - RATE_CKCTL, - .enable_reg = ARM_CKCTL, - .enable_bit = EN_DSPCK, - .rate_offset = CKCTL_DSPDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk dspmmu_ck = { - .name = "dspmmu_ck", - .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - RATE_CKCTL | ALWAYS_ENABLED, - .rate_offset = CKCTL_DSPMMUDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk dspper_ck = { - .name = "dspper_ck", - .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - RATE_CKCTL | VIRTUAL_IO_ADDRESS, - .enable_reg = DSP_IDLECT2, - .enable_bit = EN_PERCK, - .rate_offset = CKCTL_PERDIV_OFFSET, - .recalc = &omap1_ckctl_recalc_dsp_domain, - .set_rate = &omap1_clk_set_rate_dsp_domain, - .enable = &omap1_clk_enable_dsp_domain, - .disable = &omap1_clk_disable_dsp_domain, -}; - -static struct clk dspxor_ck = { - .name = "dspxor_ck", - .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - VIRTUAL_IO_ADDRESS, - .enable_reg = DSP_IDLECT2, - .enable_bit = EN_XORPCK, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_dsp_domain, - .disable = &omap1_clk_disable_dsp_domain, -}; - -static struct clk dsptim_ck = { - .name = "dsptim_ck", - .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - VIRTUAL_IO_ADDRESS, - .enable_reg = DSP_IDLECT2, - .enable_bit = EN_DSPTIMCK, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable_dsp_domain, - .disable = &omap1_clk_disable_dsp_domain, -}; - -/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ -static struct arm_idlect1_clk tc_ck = { - .clk = { - .name = "tc_ck", - .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP730 | RATE_CKCTL | - RATE_PROPAGATES | ALWAYS_ENABLED | - CLOCK_IDLE_CONTROL, - .rate_offset = CKCTL_TCDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, - }, - .idlect_shift = 6, -}; - -static struct clk arminth_ck1510 = { - .name = "arminth_ck", - .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED, - .recalc = &followparent_recalc, - /* Note: On 1510 the frequency follows TC_CK - * - * 16xx version is in MPU clocks. - */ - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk tipb_ck = { - /* No-idle controlled by "tc_ck" */ - .name = "tibp_ck", - .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk l3_ocpi_ck = { - /* No-idle controlled by "tc_ck" */ - .name = "l3_ocpi_ck", - .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX, - .enable_reg = ARM_IDLECT3, - .enable_bit = EN_OCPI_CK, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk tc1_ck = { - .name = "tc1_ck", - .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX, - .enable_reg = ARM_IDLECT3, - .enable_bit = EN_TC1_CK, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk tc2_ck = { - .name = "tc2_ck", - .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX, - .enable_reg = ARM_IDLECT3, - .enable_bit = EN_TC2_CK, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk dma_ck = { - /* No-idle controlled by "tc_ck" */ - .name = "dma_ck", - .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - ALWAYS_ENABLED, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk dma_lcdfree_ck = { - .name = "dma_lcdfree_ck", - .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct arm_idlect1_clk api_ck = { - .clk = { - .name = "api_ck", - .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IDLE_CONTROL, - .enable_reg = ARM_IDLECT2, - .enable_bit = EN_APICK, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, - }, - .idlect_shift = 8, -}; - -static struct arm_idlect1_clk lb_ck = { - .clk = { - .name = "lb_ck", - .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IDLE_CONTROL, - .enable_reg = ARM_IDLECT2, - .enable_bit = EN_LBCK, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, - }, - .idlect_shift = 4, -}; - -static struct clk rhea1_ck = { - .name = "rhea1_ck", - .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk rhea2_ck = { - .name = "rhea2_ck", - .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, - .recalc = &followparent_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk lcd_ck_16xx = { - .name = "lcd_ck", - .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL, - .enable_reg = ARM_IDLECT2, - .enable_bit = EN_LCDCK, - .rate_offset = CKCTL_LCDDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct arm_idlect1_clk lcd_ck_1510 = { - .clk = { - .name = "lcd_ck", - .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | RATE_CKCTL | - CLOCK_IDLE_CONTROL, - .enable_reg = ARM_IDLECT2, - .enable_bit = EN_LCDCK, - .rate_offset = CKCTL_LCDDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, - }, - .idlect_shift = 3, -}; - -static struct clk uart1_1510 = { - .name = "uart1_ck", - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | - ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT, - .enable_reg = MOD_CONF_CTRL_0, - .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ - .set_rate = &omap1_set_uart_rate, - .recalc = &omap1_uart_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct uart_clk uart1_16xx = { - .clk = { - .name = "uart1_ck", - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | - ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = MOD_CONF_CTRL_0, - .enable_bit = 29, - .enable = &omap1_clk_enable_uart_functional, - .disable = &omap1_clk_disable_uart_functional, - }, - .sysc_addr = 0xfffb0054, -}; - -static struct clk uart2_ck = { - .name = "uart2_ck", - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - ENABLE_REG_32BIT | ALWAYS_ENABLED | - CLOCK_NO_IDLE_PARENT, - .enable_reg = MOD_CONF_CTRL_0, - .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ - .set_rate = &omap1_set_uart_rate, - .recalc = &omap1_uart_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk uart3_1510 = { - .name = "uart3_ck", - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | - ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT, - .enable_reg = MOD_CONF_CTRL_0, - .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ - .set_rate = &omap1_set_uart_rate, - .recalc = &omap1_uart_recalc, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct uart_clk uart3_16xx = { - .clk = { - .name = "uart3_ck", - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | - ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = MOD_CONF_CTRL_0, - .enable_bit = 31, - .enable = &omap1_clk_enable_uart_functional, - .disable = &omap1_clk_disable_uart_functional, - }, - .sysc_addr = 0xfffb9854, -}; - -static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ - .name = "usb_clko", - /* Direct from ULPD, no parent */ - .rate = 6000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - RATE_FIXED | ENABLE_REG_32BIT, - .enable_reg = ULPD_CLOCK_CTRL, - .enable_bit = USB_MCLK_EN_BIT, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk usb_hhc_ck1510 = { - .name = "usb_hhc_ck", - /* Direct from ULPD, no parent */ - .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ - .flags = CLOCK_IN_OMAP1510 | - RATE_FIXED | ENABLE_REG_32BIT, - .enable_reg = MOD_CONF_CTRL_0, - .enable_bit = USB_HOST_HHC_UHOST_EN, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk usb_hhc_ck16xx = { - .name = "usb_hhc_ck", - /* Direct from ULPD, no parent */ - .rate = 48000000, - /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ - .flags = CLOCK_IN_OMAP16XX | - RATE_FIXED | ENABLE_REG_32BIT, - .enable_reg = OTG_BASE + 0x08 /* OTG_SYSCON_2 */, - .enable_bit = 8 /* UHOST_EN */, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk usb_dc_ck = { - .name = "usb_dc_ck", - /* Direct from ULPD, no parent */ - .rate = 48000000, - .flags = CLOCK_IN_OMAP16XX | RATE_FIXED, - .enable_reg = SOFT_REQ_REG, - .enable_bit = 4, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk mclk_1510 = { - .name = "mclk", - /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | RATE_FIXED, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk mclk_16xx = { - .name = "mclk", - /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .flags = CLOCK_IN_OMAP16XX, - .enable_reg = COM_CLK_DIV_CTRL_SEL, - .enable_bit = COM_ULPD_PLL_CLK_REQ, - .set_rate = &omap1_set_ext_clk_rate, - .round_rate = &omap1_round_ext_clk_rate, - .init = &omap1_init_ext_clk, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk bclk_1510 = { - .name = "bclk", - /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | RATE_FIXED, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk bclk_16xx = { - .name = "bclk", - /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .flags = CLOCK_IN_OMAP16XX, - .enable_reg = SWD_CLK_DIV_CTRL_SEL, - .enable_bit = SWD_ULPD_PLL_CLK_REQ, - .set_rate = &omap1_set_ext_clk_rate, - .round_rate = &omap1_round_ext_clk_rate, - .init = &omap1_init_ext_clk, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk mmc1_ck = { - .name = "mmc1_ck", - /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = MOD_CONF_CTRL_0, - .enable_bit = 23, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk mmc2_ck = { - .name = "mmc2_ck", - /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = CLOCK_IN_OMAP16XX | - RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = MOD_CONF_CTRL_0, - .enable_bit = 20, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk virtual_ck_mpu = { - .name = "mpu", - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - VIRTUAL_CLOCK | ALWAYS_ENABLED, - .parent = &arm_ck, /* Is smarter alias for */ - .recalc = &followparent_recalc, - .set_rate = &omap1_select_table_rate, - .round_rate = &omap1_round_to_table_rate, - .enable = &omap1_clk_enable, - .disable = &omap1_clk_disable, -}; - -static struct clk * onchip_clks[] = { - /* non-ULPD clocks */ - &ck_ref, - &ck_dpll1, - /* CK_GEN1 clocks */ - &ck_dpll1out.clk, - &arm_ck, - &armper_ck.clk, - &arm_gpio_ck, - &armxor_ck.clk, - &armtim_ck.clk, - &armwdt_ck.clk, - &arminth_ck1510, &arminth_ck16xx, - /* CK_GEN2 clocks */ - &dsp_ck, - &dspmmu_ck, - &dspper_ck, - &dspxor_ck, - &dsptim_ck, - /* CK_GEN3 clocks */ - &tc_ck.clk, - &tipb_ck, - &l3_ocpi_ck, - &tc1_ck, - &tc2_ck, - &dma_ck, - &dma_lcdfree_ck, - &api_ck.clk, - &lb_ck.clk, - &rhea1_ck, - &rhea2_ck, - &lcd_ck_16xx, - &lcd_ck_1510.clk, - /* ULPD clocks */ - &uart1_1510, - &uart1_16xx.clk, - &uart2_ck, - &uart3_1510, - &uart3_16xx.clk, - &usb_clko, - &usb_hhc_ck1510, &usb_hhc_ck16xx, - &usb_dc_ck, - &mclk_1510, &mclk_16xx, - &bclk_1510, &bclk_16xx, - &mmc1_ck, - &mmc2_ck, - /* Virtual clocks */ - &virtual_ck_mpu, -}; - /*------------------------------------------------------------------------- * Omap1 specific clock functions *-------------------------------------------------------------------------*/ diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h new file mode 100644 index 00000000000..8c429c5708c --- /dev/null +++ b/arch/arm/mach-omap1/clock.h @@ -0,0 +1,768 @@ +/* + * linux/arch/arm/mach-omap1/clock.h + * + * Copyright (C) 2004 - 2005 Nokia corporation + * Written by Tuukka Tikkanen + * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H +#define __ARCH_ARM_MACH_OMAP1_CLOCK_H + +static int omap1_clk_enable(struct clk * clk); +static void omap1_clk_disable(struct clk * clk); +static void omap1_ckctl_recalc(struct clk * clk); +static void omap1_watchdog_recalc(struct clk * clk); +static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); +static int omap1_clk_enable_dsp_domain(struct clk * clk); +static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); +static void omap1_clk_disable_dsp_domain(struct clk * clk); +static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); +static void omap1_uart_recalc(struct clk * clk); +static int omap1_clk_enable_uart_functional(struct clk * clk); +static void omap1_clk_disable_uart_functional(struct clk * clk); +static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); +static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); +static void omap1_init_ext_clk(struct clk * clk); +static int omap1_select_table_rate(struct clk * clk, unsigned long rate); +static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); +static int omap1_clk_use(struct clk *clk); +static void omap1_clk_unuse(struct clk *clk); + +struct mpu_rate { + unsigned long rate; + unsigned long xtal; + unsigned long pll_rate; + __u16 ckctl_val; + __u16 dpllctl_val; +}; + +struct uart_clk { + struct clk clk; + unsigned long sysc_addr; +}; + +/* Provide a method for preventing idling some ARM IDLECT clocks */ +struct arm_idlect1_clk { + struct clk clk; + unsigned long no_idle_count; + __u8 idlect_shift; +}; + +/* ARM_CKCTL bit shifts */ +#define CKCTL_PERDIV_OFFSET 0 +#define CKCTL_LCDDIV_OFFSET 2 +#define CKCTL_ARMDIV_OFFSET 4 +#define CKCTL_DSPDIV_OFFSET 6 +#define CKCTL_TCDIV_OFFSET 8 +#define CKCTL_DSPMMUDIV_OFFSET 10 +/*#define ARM_TIMXO 12*/ +#define EN_DSPCK 13 +/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ +/* DSP_CKCTL bit shifts */ +#define CKCTL_DSPPERDIV_OFFSET 0 + +/* ARM_IDLECT2 bit shifts */ +#define EN_WDTCK 0 +#define EN_XORPCK 1 +#define EN_PERCK 2 +#define EN_LCDCK 3 +#define EN_LBCK 4 /* Not on 1610/1710 */ +/*#define EN_HSABCK 5*/ +#define EN_APICK 6 +#define EN_TIMCK 7 +#define DMACK_REQ 8 +#define EN_GPIOCK 9 /* Not on 1610/1710 */ +/*#define EN_LBFREECK 10*/ +#define EN_CKOUT_ARM 11 + +/* ARM_IDLECT3 bit shifts */ +#define EN_OCPI_CK 0 +#define EN_TC1_CK 2 +#define EN_TC2_CK 4 + +/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ +#define EN_DSPTIMCK 5 + +/* Various register defines for clock controls scattered around OMAP chip */ +#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ +#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ +#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ +#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ +#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 +#define COM_CLK_DIV_CTRL_SEL 0xfffe0878 +#define SOFT_REQ_REG 0xfffe0834 +#define SOFT_REQ_REG2 0xfffe0880 + +/*------------------------------------------------------------------------- + * Omap1 MPU rate table + *-------------------------------------------------------------------------*/ +static struct mpu_rate rate_table[] = { + /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL + * NOTE: Comment order here is different from bits in CKCTL value: + * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv + */ +#if defined(CONFIG_OMAP_ARM_216MHZ) + { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ +#endif +#if defined(CONFIG_OMAP_ARM_195MHZ) + { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ +#endif +#if defined(CONFIG_OMAP_ARM_192MHZ) + { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ + { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ + { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ + { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ + { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ +#endif +#if defined(CONFIG_OMAP_ARM_182MHZ) + { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ +#endif +#if defined(CONFIG_OMAP_ARM_168MHZ) + { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ +#endif +#if defined(CONFIG_OMAP_ARM_150MHZ) + { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ +#endif +#if defined(CONFIG_OMAP_ARM_120MHZ) + { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ +#endif +#if defined(CONFIG_OMAP_ARM_96MHZ) + { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ +#endif +#if defined(CONFIG_OMAP_ARM_60MHZ) + { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ +#endif +#if defined(CONFIG_OMAP_ARM_30MHZ) + { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ +#endif + { 0, 0, 0, 0, 0 }, +}; + +/*------------------------------------------------------------------------- + * Omap1 clocks + *-------------------------------------------------------------------------*/ + +static struct clk ck_ref = { + .name = "ck_ref", + .rate = 12000000, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + ALWAYS_ENABLED, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk ck_dpll1 = { + .name = "ck_dpll1", + .parent = &ck_ref, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + RATE_PROPAGATES | ALWAYS_ENABLED, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct arm_idlect1_clk ck_dpll1out = { + .clk = { + .name = "ck_dpll1out", + .parent = &ck_dpll1, + .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL, + .enable_reg = ARM_IDLECT2, + .enable_bit = EN_CKOUT_ARM, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, + }, + .idlect_shift = 12, +}; + +static struct clk arm_ck = { + .name = "arm_ck", + .parent = &ck_dpll1, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED, + .rate_offset = CKCTL_ARMDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct arm_idlect1_clk armper_ck = { + .clk = { + .name = "armper_ck", + .parent = &ck_dpll1, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + RATE_CKCTL | CLOCK_IDLE_CONTROL, + .enable_reg = ARM_IDLECT2, + .enable_bit = EN_PERCK, + .rate_offset = CKCTL_PERDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, + }, + .idlect_shift = 2, +}; + +static struct clk arm_gpio_ck = { + .name = "arm_gpio_ck", + .parent = &ck_dpll1, + .flags = CLOCK_IN_OMAP1510, + .enable_reg = ARM_IDLECT2, + .enable_bit = EN_GPIOCK, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct arm_idlect1_clk armxor_ck = { + .clk = { + .name = "armxor_ck", + .parent = &ck_ref, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + CLOCK_IDLE_CONTROL, + .enable_reg = ARM_IDLECT2, + .enable_bit = EN_XORPCK, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, + }, + .idlect_shift = 1, +}; + +static struct arm_idlect1_clk armtim_ck = { + .clk = { + .name = "armtim_ck", + .parent = &ck_ref, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + CLOCK_IDLE_CONTROL, + .enable_reg = ARM_IDLECT2, + .enable_bit = EN_TIMCK, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, + }, + .idlect_shift = 9, +}; + +static struct arm_idlect1_clk armwdt_ck = { + .clk = { + .name = "armwdt_ck", + .parent = &ck_ref, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + CLOCK_IDLE_CONTROL, + .enable_reg = ARM_IDLECT2, + .enable_bit = EN_WDTCK, + .recalc = &omap1_watchdog_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, + }, + .idlect_shift = 0, +}; + +static struct clk arminth_ck16xx = { + .name = "arminth_ck", + .parent = &arm_ck, + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .recalc = &followparent_recalc, + /* Note: On 16xx the frequency can be divided by 2 by programming + * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 + * + * 1510 version is in TC clocks. + */ + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk dsp_ck = { + .name = "dsp_ck", + .parent = &ck_dpll1, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + RATE_CKCTL, + .enable_reg = ARM_CKCTL, + .enable_bit = EN_DSPCK, + .rate_offset = CKCTL_DSPDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk dspmmu_ck = { + .name = "dspmmu_ck", + .parent = &ck_dpll1, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + RATE_CKCTL | ALWAYS_ENABLED, + .rate_offset = CKCTL_DSPMMUDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk dspper_ck = { + .name = "dspper_ck", + .parent = &ck_dpll1, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + RATE_CKCTL | VIRTUAL_IO_ADDRESS, + .enable_reg = DSP_IDLECT2, + .enable_bit = EN_PERCK, + .rate_offset = CKCTL_PERDIV_OFFSET, + .recalc = &omap1_ckctl_recalc_dsp_domain, + .set_rate = &omap1_clk_set_rate_dsp_domain, + .enable = &omap1_clk_enable_dsp_domain, + .disable = &omap1_clk_disable_dsp_domain, +}; + +static struct clk dspxor_ck = { + .name = "dspxor_ck", + .parent = &ck_ref, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + VIRTUAL_IO_ADDRESS, + .enable_reg = DSP_IDLECT2, + .enable_bit = EN_XORPCK, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable_dsp_domain, + .disable = &omap1_clk_disable_dsp_domain, +}; + +static struct clk dsptim_ck = { + .name = "dsptim_ck", + .parent = &ck_ref, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + VIRTUAL_IO_ADDRESS, + .enable_reg = DSP_IDLECT2, + .enable_bit = EN_DSPTIMCK, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable_dsp_domain, + .disable = &omap1_clk_disable_dsp_domain, +}; + +/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ +static struct arm_idlect1_clk tc_ck = { + .clk = { + .name = "tc_ck", + .parent = &ck_dpll1, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + CLOCK_IN_OMAP730 | RATE_CKCTL | + RATE_PROPAGATES | ALWAYS_ENABLED | + CLOCK_IDLE_CONTROL, + .rate_offset = CKCTL_TCDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, + }, + .idlect_shift = 6, +}; + +static struct clk arminth_ck1510 = { + .name = "arminth_ck", + .parent = &tc_ck.clk, + .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED, + .recalc = &followparent_recalc, + /* Note: On 1510 the frequency follows TC_CK + * + * 16xx version is in MPU clocks. + */ + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk tipb_ck = { + /* No-idle controlled by "tc_ck" */ + .name = "tibp_ck", + .parent = &tc_ck.clk, + .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk l3_ocpi_ck = { + /* No-idle controlled by "tc_ck" */ + .name = "l3_ocpi_ck", + .parent = &tc_ck.clk, + .flags = CLOCK_IN_OMAP16XX, + .enable_reg = ARM_IDLECT3, + .enable_bit = EN_OCPI_CK, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk tc1_ck = { + .name = "tc1_ck", + .parent = &tc_ck.clk, + .flags = CLOCK_IN_OMAP16XX, + .enable_reg = ARM_IDLECT3, + .enable_bit = EN_TC1_CK, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk tc2_ck = { + .name = "tc2_ck", + .parent = &tc_ck.clk, + .flags = CLOCK_IN_OMAP16XX, + .enable_reg = ARM_IDLECT3, + .enable_bit = EN_TC2_CK, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk dma_ck = { + /* No-idle controlled by "tc_ck" */ + .name = "dma_ck", + .parent = &tc_ck.clk, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + ALWAYS_ENABLED, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk dma_lcdfree_ck = { + .name = "dma_lcdfree_ck", + .parent = &tc_ck.clk, + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct arm_idlect1_clk api_ck = { + .clk = { + .name = "api_ck", + .parent = &tc_ck.clk, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + CLOCK_IDLE_CONTROL, + .enable_reg = ARM_IDLECT2, + .enable_bit = EN_APICK, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, + }, + .idlect_shift = 8, +}; + +static struct arm_idlect1_clk lb_ck = { + .clk = { + .name = "lb_ck", + .parent = &tc_ck.clk, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IDLE_CONTROL, + .enable_reg = ARM_IDLECT2, + .enable_bit = EN_LBCK, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, + }, + .idlect_shift = 4, +}; + +static struct clk rhea1_ck = { + .name = "rhea1_ck", + .parent = &tc_ck.clk, + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk rhea2_ck = { + .name = "rhea2_ck", + .parent = &tc_ck.clk, + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk lcd_ck_16xx = { + .name = "lcd_ck", + .parent = &ck_dpll1, + .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL, + .enable_reg = ARM_IDLECT2, + .enable_bit = EN_LCDCK, + .rate_offset = CKCTL_LCDDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct arm_idlect1_clk lcd_ck_1510 = { + .clk = { + .name = "lcd_ck", + .parent = &ck_dpll1, + .flags = CLOCK_IN_OMAP1510 | RATE_CKCTL | + CLOCK_IDLE_CONTROL, + .enable_reg = ARM_IDLECT2, + .enable_bit = EN_LCDCK, + .rate_offset = CKCTL_LCDDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, + }, + .idlect_shift = 3, +}; + +static struct clk uart1_1510 = { + .name = "uart1_ck", + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 12000000, + .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | + ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT, + .enable_reg = MOD_CONF_CTRL_0, + .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ + .set_rate = &omap1_set_uart_rate, + .recalc = &omap1_uart_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct uart_clk uart1_16xx = { + .clk = { + .name = "uart1_ck", + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | + ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = MOD_CONF_CTRL_0, + .enable_bit = 29, + .enable = &omap1_clk_enable_uart_functional, + .disable = &omap1_clk_disable_uart_functional, + }, + .sysc_addr = 0xfffb0054, +}; + +static struct clk uart2_ck = { + .name = "uart2_ck", + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 12000000, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + ENABLE_REG_32BIT | ALWAYS_ENABLED | + CLOCK_NO_IDLE_PARENT, + .enable_reg = MOD_CONF_CTRL_0, + .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ + .set_rate = &omap1_set_uart_rate, + .recalc = &omap1_uart_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk uart3_1510 = { + .name = "uart3_ck", + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 12000000, + .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | + ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT, + .enable_reg = MOD_CONF_CTRL_0, + .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ + .set_rate = &omap1_set_uart_rate, + .recalc = &omap1_uart_recalc, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct uart_clk uart3_16xx = { + .clk = { + .name = "uart3_ck", + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | + ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = MOD_CONF_CTRL_0, + .enable_bit = 31, + .enable = &omap1_clk_enable_uart_functional, + .disable = &omap1_clk_disable_uart_functional, + }, + .sysc_addr = 0xfffb9854, +}; + +static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ + .name = "usb_clko", + /* Direct from ULPD, no parent */ + .rate = 6000000, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + RATE_FIXED | ENABLE_REG_32BIT, + .enable_reg = ULPD_CLOCK_CTRL, + .enable_bit = USB_MCLK_EN_BIT, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk usb_hhc_ck1510 = { + .name = "usb_hhc_ck", + /* Direct from ULPD, no parent */ + .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ + .flags = CLOCK_IN_OMAP1510 | + RATE_FIXED | ENABLE_REG_32BIT, + .enable_reg = MOD_CONF_CTRL_0, + .enable_bit = USB_HOST_HHC_UHOST_EN, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk usb_hhc_ck16xx = { + .name = "usb_hhc_ck", + /* Direct from ULPD, no parent */ + .rate = 48000000, + /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ + .flags = CLOCK_IN_OMAP16XX | + RATE_FIXED | ENABLE_REG_32BIT, + .enable_reg = OTG_BASE + 0x08 /* OTG_SYSCON_2 */, + .enable_bit = 8 /* UHOST_EN */, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk usb_dc_ck = { + .name = "usb_dc_ck", + /* Direct from ULPD, no parent */ + .rate = 48000000, + .flags = CLOCK_IN_OMAP16XX | RATE_FIXED, + .enable_reg = SOFT_REQ_REG, + .enable_bit = 4, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk mclk_1510 = { + .name = "mclk", + /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .rate = 12000000, + .flags = CLOCK_IN_OMAP1510 | RATE_FIXED, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk mclk_16xx = { + .name = "mclk", + /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .flags = CLOCK_IN_OMAP16XX, + .enable_reg = COM_CLK_DIV_CTRL_SEL, + .enable_bit = COM_ULPD_PLL_CLK_REQ, + .set_rate = &omap1_set_ext_clk_rate, + .round_rate = &omap1_round_ext_clk_rate, + .init = &omap1_init_ext_clk, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk bclk_1510 = { + .name = "bclk", + /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .rate = 12000000, + .flags = CLOCK_IN_OMAP1510 | RATE_FIXED, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk bclk_16xx = { + .name = "bclk", + /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .flags = CLOCK_IN_OMAP16XX, + .enable_reg = SWD_CLK_DIV_CTRL_SEL, + .enable_bit = SWD_ULPD_PLL_CLK_REQ, + .set_rate = &omap1_set_ext_clk_rate, + .round_rate = &omap1_round_ext_clk_rate, + .init = &omap1_init_ext_clk, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk mmc1_ck = { + .name = "mmc1_ck", + /* Functional clock is direct from ULPD, interface clock is ARMPER */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = MOD_CONF_CTRL_0, + .enable_bit = 23, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk mmc2_ck = { + .name = "mmc2_ck", + /* Functional clock is direct from ULPD, interface clock is ARMPER */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = CLOCK_IN_OMAP16XX | + RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = MOD_CONF_CTRL_0, + .enable_bit = 20, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk virtual_ck_mpu = { + .name = "mpu", + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + VIRTUAL_CLOCK | ALWAYS_ENABLED, + .parent = &arm_ck, /* Is smarter alias for */ + .recalc = &followparent_recalc, + .set_rate = &omap1_select_table_rate, + .round_rate = &omap1_round_to_table_rate, + .enable = &omap1_clk_enable, + .disable = &omap1_clk_disable, +}; + +static struct clk * onchip_clks[] = { + /* non-ULPD clocks */ + &ck_ref, + &ck_dpll1, + /* CK_GEN1 clocks */ + &ck_dpll1out.clk, + &arm_ck, + &armper_ck.clk, + &arm_gpio_ck, + &armxor_ck.clk, + &armtim_ck.clk, + &armwdt_ck.clk, + &arminth_ck1510, &arminth_ck16xx, + /* CK_GEN2 clocks */ + &dsp_ck, + &dspmmu_ck, + &dspper_ck, + &dspxor_ck, + &dsptim_ck, + /* CK_GEN3 clocks */ + &tc_ck.clk, + &tipb_ck, + &l3_ocpi_ck, + &tc1_ck, + &tc2_ck, + &dma_ck, + &dma_lcdfree_ck, + &api_ck.clk, + &lb_ck.clk, + &rhea1_ck, + &rhea2_ck, + &lcd_ck_16xx, + &lcd_ck_1510.clk, + /* ULPD clocks */ + &uart1_1510, + &uart1_16xx.clk, + &uart2_ck, + &uart3_1510, + &uart3_16xx.clk, + &usb_clko, + &usb_hhc_ck1510, &usb_hhc_ck16xx, + &usb_dc_ck, + &mclk_1510, &mclk_16xx, + &bclk_1510, &bclk_16xx, + &mmc1_ck, + &mmc2_ck, + /* Virtual clocks */ + &virtual_ck_mpu, +}; + +#endif diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 086e1a4bc44..61ac4a790c5 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -30,7 +30,7 @@ static struct clk_functions *arch_clock; * Standard clock functions defined in asm/hardware/clock.h *-------------------------------------------------------------------------*/ -struct clk *clk_get(struct device *dev, const char *id) +struct clk * clk_get(struct device *dev, const char *id) { struct clk *p, *clk = ERR_PTR(-ENOENT); @@ -155,6 +155,8 @@ EXPORT_SYMBOL(clk_get_parent); /*------------------------------------------------------------------------- * OMAP specific clock functions shared between omap1 and omap2 *-------------------------------------------------------------------------*/ + +/* Used for clocks that always have same value as the parent clock */ void followparent_recalc(struct clk * clk) { clk->rate = clk->parent->rate; diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index 61dc344d76c..a4e8042ccdf 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -21,11 +21,12 @@ struct clk { const char *name; struct clk *parent; unsigned long rate; - __s8 usecount; - __u16 flags; + __u32 flags; __u32 enable_reg; __u8 enable_bit; __u8 rate_offset; + __u8 src_offset; + __s8 usecount; void (*recalc)(struct clk *); int (*set_rate)(struct clk *, unsigned long); long (*round_rate)(struct clk *, unsigned long); @@ -53,85 +54,32 @@ extern void clk_unregister(struct clk *clk); extern void propagate_rate(struct clk *clk); extern void followparent_recalc(struct clk * clk); -/*------------------------------------------------------------------------- - * Defines for omap1 clocks - *-------------------------------------------------------------------------*/ - /* Clock flags */ -#define RATE_CKCTL 1 -#define RATE_FIXED 2 -#define RATE_PROPAGATES 4 -#define VIRTUAL_CLOCK 8 -#define ALWAYS_ENABLED 16 -#define ENABLE_REG_32BIT 32 -#define CLOCK_IN_OMAP16XX 64 -#define CLOCK_IN_OMAP1510 128 -#define CLOCK_IN_OMAP730 256 -#define VIRTUAL_IO_ADDRESS 512 -#define CLOCK_IDLE_CONTROL 1024 -#define CLOCK_NO_IDLE_PARENT 2048 - -/* ARM_CKCTL bit shifts */ -#define CKCTL_PERDIV_OFFSET 0 -#define CKCTL_LCDDIV_OFFSET 2 -#define CKCTL_ARMDIV_OFFSET 4 -#define CKCTL_DSPDIV_OFFSET 6 -#define CKCTL_TCDIV_OFFSET 8 -#define CKCTL_DSPMMUDIV_OFFSET 10 -/*#define ARM_TIMXO 12*/ -#define EN_DSPCK 13 -/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ -/* DSP_CKCTL bit shifts */ -#define CKCTL_DSPPERDIV_OFFSET 0 - -/* ARM_IDLECT1 bit shifts */ -/*#define IDLWDT_ARM 0*/ -/*#define IDLXORP_ARM 1*/ -/*#define IDLPER_ARM 2*/ -/*#define IDLLCD_ARM 3*/ -/*#define IDLLB_ARM 4*/ -/*#define IDLHSAB_ARM 5*/ -/*#define IDLIF_ARM 6*/ -/*#define IDLDPLL_ARM 7*/ -/*#define IDLAPI_ARM 8*/ -/*#define IDLTIM_ARM 9*/ -/*#define SETARM_IDLE 11*/ - -/* ARM_IDLECT2 bit shifts */ -#define EN_WDTCK 0 -#define EN_XORPCK 1 -#define EN_PERCK 2 -#define EN_LCDCK 3 -#define EN_LBCK 4 /* Not on 1610/1710 */ -/*#define EN_HSABCK 5*/ -#define EN_APICK 6 -#define EN_TIMCK 7 -#define DMACK_REQ 8 -#define EN_GPIOCK 9 /* Not on 1610/1710 */ -/*#define EN_LBFREECK 10*/ -#define EN_CKOUT_ARM 11 - -/* ARM_IDLECT3 bit shifts */ -#define EN_OCPI_CK 0 -#define EN_TC1_CK 2 -#define EN_TC2_CK 4 - -/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ -#define EN_DSPTIMCK 5 - -/* Various register defines for clock controls scattered around OMAP chip */ -#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ -#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ -#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ -#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ -#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 -#define COM_CLK_DIV_CTRL_SEL 0xfffe0878 -#define SOFT_REQ_REG 0xfffe0834 -#define SOFT_REQ_REG2 0xfffe0880 - -/*------------------------------------------------------------------------- - * Defines for omap2 clocks - *-------------------------------------------------------------------------*/ - +#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ +#define RATE_FIXED (1 << 1) /* Fixed clock rate */ +#define RATE_PROPAGATES (1 << 2) /* Program children too */ +#define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */ +#define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */ +#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ +#define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */ +#define CLOCK_IDLE_CONTROL (1 << 7) +#define CLOCK_NO_IDLE_PARENT (1 << 8) +#define DELAYED_APP (1 << 9) /* Delay application of clock */ +#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ +#define CM_MPU_SEL1 (1 << 11) /* Domain divider/source */ +#define CM_DSP_SEL1 (1 << 12) +#define CM_GFX_SEL1 (1 << 13) +#define CM_MODEM_SEL1 (1 << 14) +#define CM_CORE_SEL1 (1 << 15) /* Sets divider for many */ +#define CM_CORE_SEL2 (1 << 16) /* sets parent for GPT */ +#define CM_WKUP_SEL1 (1 << 17) +#define CM_PLL_SEL1 (1 << 18) +#define CM_PLL_SEL2 (1 << 19) +#define CM_SYSCLKOUT_SEL1 (1 << 20) +#define CLOCK_IN_OMAP730 (1 << 21) +#define CLOCK_IN_OMAP1510 (1 << 22) +#define CLOCK_IN_OMAP16XX (1 << 23) +#define CLOCK_IN_OMAP242X (1 << 24) +#define CLOCK_IN_OMAP243X (1 << 25) #endif -- 2.41.1