From 8b1f0bd44fe490ec631230c8c040753a2bda8caa Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 25 Sep 2008 08:38:46 -0600 Subject: [PATCH] OMAP3 clock: put DPLL into bypass if bypass rate = clk->rate, not hardware rate When a non-CORE DPLL is enabled via omap3_noncore_dpll_enable(), use the user's desired rate in clk->rate to determine whether to put the DPLL into bypass or lock mode, rather than reading the DPLL's current idle state from its hardware registers. This fixes a bug observed when leaving retention. Non-CORE DPLLs were not being relocked when downstream clocks re-enabled; rather, the DPLL entered bypass mode. Problem reported by Tero Kristo . Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock34xx.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index c89d6bcb197..df258f76203 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -281,9 +281,7 @@ static int omap3_noncore_dpll_enable(struct clk *clk) if (!dd) return -EINVAL; - rate = omap2_get_dpll_rate(clk); - - if (dd->bypass_clk->rate == rate) + if (clk->rate == dd->bypass_clk->rate) r = _omap3_noncore_dpll_bypass(clk); else r = _omap3_noncore_dpll_lock(clk); -- 2.41.1