From 868d3af23f43359b24d11d3a9db849a3dd8a3849 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 2 Aug 2007 12:10:21 -0600 Subject: [PATCH] omap2 clock: use dedicated omap2_dpll_recalc() for DPLL recalc func dpll_ck is not a clksel clock, and so it does not really fit well into omap2_clksel_recalc(). Split off its recalc code into its own function, omap2_dpll_recalc(). Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock.c | 17 +++++++++-------- arch/arm/mach-omap2/clock.h | 3 ++- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 827f55c2709..0df6bb790b3 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -387,6 +387,13 @@ static u32 omap2_dpll_round_rate(unsigned long target_rate) } +static void omap2_dpll_recalc(struct clk *clk) +{ + clk->rate = omap2_get_dpll_rate(clk); + + propagate_rate(clk); +} + /* * Used for clocks that are part of CLKSEL_xyz governed clocks. * REVISIT: Maybe change to use clk->enable() functions like on omap1? @@ -396,12 +403,6 @@ static void omap2_clksel_recalc(struct clk * clk) u32 fixed = 0, div = 0; u32 clksel1_core; - if (clk == &dpll_ck) { - clk->rate = omap2_get_dpll_rate(clk); - fixed = 1; - div = 0; - } - if (clk == &iva1_mpu_int_ifck) { div = 2; fixed = 1; @@ -594,7 +595,7 @@ static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate) omap2_init_memory_params(omap2_dll_force_needed()); omap2_reprogram_sdrc(done_rate, 0); } - omap2_clksel_recalc(&dpll_ck); + omap2_dpll_recalc(&dpll_ck); ret = 0; dpll_exit: @@ -1093,7 +1094,7 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate) local_irq_restore(flags); } - omap2_clksel_recalc(&dpll_ck); + omap2_dpll_recalc(&dpll_ck); return 0; } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 76ac124733f..5991aba12d4 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -33,6 +33,7 @@ static void omap2_clk_disable(struct clk *clk); static void omap2_sys_clk_recalc(struct clk * clk); static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val); static u32 omap2_clksel_get_divisor(struct clk *clk); +static void omap2_dpll_recalc(struct clk *clk); #define RATE_IN_242X (1 << 0) #define RATE_IN_243X (1 << 1) @@ -632,7 +633,7 @@ static struct clk dpll_ck = { .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1 | ALWAYS_ENABLED, - .recalc = &omap2_clksel_recalc, + .recalc = &omap2_dpll_recalc, }; static struct clk apll96_ck = { -- 2.41.1