From 7d19267b8d1e12c0baebf9be96e04cddffe63f67 Mon Sep 17 00:00:00 2001 From: Elias Oltmanns Date: Wed, 29 Oct 2008 14:25:42 +0100 Subject: [PATCH] ath5k: Fix reset sequence for AR5212 in general and RF5111 in particular Take care to handle register 0xa228 exactly as in the HAL released by Atheros. This change is required to make ath5k work again on my system since commit 2203d6be (ath5k: Misc hw_reset updates), thus fixing a regression in 2.6.27 and therefore hopefully eligible for inclusion into a stable release. v2: Only overwrite initial register values on later revisions of AR5212 chips. v3: Use standard macros to manipulate the register. Signed-off-by: Elias Oltmanns Signed-off-by: John W. Linville --- drivers/net/wireless/ath5k/initvals.c | 2 ++ drivers/net/wireless/ath5k/reset.c | 22 +++++++--------------- 2 files changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/net/wireless/ath5k/initvals.c b/drivers/net/wireless/ath5k/initvals.c index ea2e1a20b49..ceaa6c475c0 100644 --- a/drivers/net/wireless/ath5k/initvals.c +++ b/drivers/net/wireless/ath5k/initvals.c @@ -806,6 +806,8 @@ static const struct ath5k_ini_mode ar5212_rf5111_ini_mode_end[] = { { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHY(642), { 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, + { 0xa228, + { 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5 } }, { 0xa23c, { 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af } }, }; diff --git a/drivers/net/wireless/ath5k/reset.c b/drivers/net/wireless/ath5k/reset.c index 8f1886834e6..1b6d45b6772 100644 --- a/drivers/net/wireless/ath5k/reset.c +++ b/drivers/net/wireless/ath5k/reset.c @@ -537,9 +537,10 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, mdelay(1); /* - * Write some more initial register settings + * Write some more initial register settings for revised chips */ - if (ah->ah_version == AR5K_AR5212) { + if (ah->ah_version == AR5K_AR5212 && + ah->ah_phy_revision > 0x41) { ath5k_hw_reg_write(ah, 0x0002a002, 0x982c); if (channel->hw_value == CHANNEL_G) @@ -558,19 +559,10 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, else ath5k_hw_reg_write(ah, 0x00000000, 0x994c); - /* Some bits are disabled here, we know nothing about - * register 0xa228 yet, most of the times this ends up - * with a value 0x9b5 -haven't seen any dump with - * a different value- */ - /* Got this from decompiling binary HAL */ - data = ath5k_hw_reg_read(ah, 0xa228); - data &= 0xfffffdff; - ath5k_hw_reg_write(ah, data, 0xa228); - - data = ath5k_hw_reg_read(ah, 0xa228); - data &= 0xfffe03ff; - ath5k_hw_reg_write(ah, data, 0xa228); - data = 0; + /* Got this from legacy-hal */ + AR5K_REG_DISABLE_BITS(ah, 0xa228, 0x200); + + AR5K_REG_MASKED_BITS(ah, 0xa228, 0x800, 0xfffe03ff); /* Just write 0x9b5 ? */ /* ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); */ -- 2.41.1