From 7add6d0972c615c58bf3de35a3eb1e216c2eab13 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 10 Apr 2008 00:40:14 +0000 Subject: [PATCH] ARM: OMAP2: Remove unnecessary abstraction functions for CM and PRM Remove cm_write_reg(), cm_read_reg(), prm_write_reg(), prm_read_reg() and replace them with __raw_readl() and __raw_writel(). Based on comments from RMK. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock.c | 22 +++++++++--------- arch/arm/mach-omap2/clock24xx.c | 4 ++-- arch/arm/mach-omap2/clock34xx.c | 6 ++--- arch/arm/mach-omap2/cm.h | 40 +++++++++++++-------------------- arch/arm/mach-omap2/memory.c | 2 +- arch/arm/mach-omap2/pm.c | 22 +++++++++--------- arch/arm/mach-omap2/prm.h | 31 +++++++++---------------- 7 files changed, 54 insertions(+), 73 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 250a33f3433..bc703eaee13 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -102,7 +102,7 @@ u32 omap2_get_dpll_rate(struct clk *clk) if (!dd) return 0; - dpll = cm_read_reg(dd->mult_div1_reg); + dpll = __raw_readl(dd->mult_div1_reg); dpll_mult = dpll & dd->mult_mask; dpll_mult >>= __ffs(dd->mult_mask); dpll_div = dpll & dd->div1_mask; @@ -153,7 +153,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) } /* Wait for lock */ - while (((cm_read_reg(reg) & mask) != ena) && + while (((__raw_readl(reg) & mask) != ena) && (i++ < MAX_CLOCK_ENABLE_WAIT)) { udelay(1); } @@ -211,7 +211,7 @@ static void omap2_clk_wait_ready(struct clk *clk) /* Check if both functional and interface clocks * are running. */ bit = 1 << clk->enable_bit; - if (!(cm_read_reg(other_reg) & bit)) + if (!(__raw_readl(other_reg) & bit)) return; st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */ @@ -237,12 +237,12 @@ int _omap2_clk_enable(struct clk *clk) return 0; /* REVISIT: -EINVAL */ } - regval32 = cm_read_reg(clk->enable_reg); + regval32 = __raw_readl(clk->enable_reg); if (clk->flags & INVERT_ENABLE) regval32 &= ~(1 << clk->enable_bit); else regval32 |= (1 << clk->enable_bit); - cm_write_reg(regval32, clk->enable_reg); + __raw_writel(regval32, clk->enable_reg); wmb(); omap2_clk_wait_ready(clk); @@ -273,12 +273,12 @@ void _omap2_clk_disable(struct clk *clk) return; } - regval32 = cm_read_reg(clk->enable_reg); + regval32 = __raw_readl(clk->enable_reg); if (clk->flags & INVERT_ENABLE) regval32 |= (1 << clk->enable_bit); else regval32 &= ~(1 << clk->enable_bit); - cm_write_reg(regval32, clk->enable_reg); + __raw_writel(regval32, clk->enable_reg); wmb(); } @@ -569,7 +569,7 @@ u32 omap2_clksel_get_divisor(struct clk *clk) if (div_addr == 0) return 0; - field_val = cm_read_reg(div_addr) & field_mask; + field_val = __raw_readl(div_addr) & field_mask; field_val >>= __ffs(field_mask); return omap2_clksel_to_divisor(clk, field_val); @@ -599,7 +599,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) clk->rate = clk->parent->rate / new_div; if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { - prm_write_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); + __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); wmb(); } @@ -695,7 +695,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) wmb(); if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { - prm_write_reg(OMAP24XX_VALID_CONFIG, + __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); wmb(); } @@ -731,7 +731,7 @@ void omap2_clk_disable_unused(struct clk *clk) v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; - regval32 = cm_read_reg(clk->enable_reg); + regval32 = __raw_readl(clk->enable_reg); if ((regval32 & (1 << clk->enable_bit)) == v) return; diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index 5ea48ff8d4e..6c2c9990965 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -203,7 +203,7 @@ static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate) if (!dd) goto dpll_exit; - tmpset.cm_clksel1_pll = cm_read_reg(dd->mult_div1_reg); + tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); tmpset.cm_clksel1_pll &= ~(dd->mult_mask | dd->div1_mask); div = ((curr_prcm_set->xtal_speed / 1000000) - 1); @@ -442,7 +442,7 @@ static u32 omap2_get_sysclkdiv(void) { u32 div; - div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL); + div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); div &= OMAP_SYSCLKDIV_MASK; div >>= OMAP_SYSCLKDIV_SHIFT; diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 80cc4447065..a263db90c53 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -82,7 +82,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) state <<= dd->idlest_bit; idlest_mask = 1 << dd->idlest_bit; - while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) && + while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) && i < MAX_DPLL_WAIT_TRIES) { i++; udelay(1); @@ -285,7 +285,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk) dd = clk->dpll_data; - v = cm_read_reg(dd->autoidle_reg); + v = __raw_readl(dd->autoidle_reg); v &= dd->autoidle_mask; v >>= __ffs(dd->autoidle_mask); @@ -367,7 +367,7 @@ static void omap3_clkoutx2_recalc(struct clk *clk) WARN_ON(!dd->control_reg || !dd->enable_mask); - v = cm_read_reg(dd->control_reg) & dd->enable_mask; + v = __raw_readl(dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); if (v != DPLL_LOCKED) clk->rate = clk->parent->rate; diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index aff3f7970cf..dc9cf850683 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -43,29 +43,17 @@ #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) #ifndef __ASSEMBLER__ -/* Clock management global register get/set */ - -static void __attribute__((unused)) cm_write_reg(u32 val, void __iomem *addr) -{ - pr_debug("cm_write_reg: writing 0x%0x to 0x%0x\n", val, (u32)addr); - - __raw_writel(val, addr); -} - -static u32 __attribute__((unused)) cm_read_reg(void __iomem *addr) -{ - return __raw_readl(addr); -} /* Read-modify-write bits in a CM register */ -static u32 __attribute__((unused)) cm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *va) +static __inline__ u32 __attribute__((unused)) cm_rmw_reg_bits(u32 mask, + u32 bits, void __iomem *va) { u32 v; - v = cm_read_reg(va); + v = __raw_readl(va); v &= ~mask; v |= bits; - cm_write_reg(v, va); + __raw_writel(v, va); return v; } @@ -128,29 +116,33 @@ static u32 __attribute__((unused)) cm_rmw_reg_bits(u32 mask, u32 bits, void __io /* Clock management domain register get/set */ #ifndef __ASSEMBLER__ -static void __attribute__((unused)) cm_write_mod_reg(u32 val, s16 module, - s16 idx) +static __inline__ void __attribute__((unused)) cm_write_mod_reg(u32 val, + s16 module, s16 idx) { - cm_write_reg(val, OMAP_CM_REGADDR(module, idx)); + __raw_writel(val, OMAP_CM_REGADDR(module, idx)); } -static u32 __attribute__((unused)) cm_read_mod_reg(s16 module, s16 idx) +static __inline__ u32 __attribute__((unused)) cm_read_mod_reg(s16 module, + s16 idx) { - return cm_read_reg(OMAP_CM_REGADDR(module, idx)); + return __raw_readl(OMAP_CM_REGADDR(module, idx)); } /* Read-modify-write bits in a CM register (by domain) */ -static inline u32 __attribute__((unused)) cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) +static __inline__ u32 __attribute__((unused)) cm_rmw_mod_reg_bits(u32 mask, + u32 bits, s16 module, s16 idx) { return cm_rmw_reg_bits(mask, bits, OMAP_CM_REGADDR(module, idx)); } -static inline u32 __attribute__((unused)) cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) +static __inline__ u32 __attribute__((unused)) cm_set_mod_reg_bits(u32 bits, + s16 module, s16 idx) { return cm_rmw_mod_reg_bits(bits, bits, module, idx); } -static inline u32 __attribute__((unused)) cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +static __inline__ u32 __attribute__((unused)) cm_clear_mod_reg_bits(u32 bits, + s16 module, s16 idx) { return cm_rmw_mod_reg_bits(bits, 0x0, module, idx); } diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index 412357e97e0..12479081881 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c @@ -93,7 +93,7 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force) m_type = omap2_memory_get_type(); local_irq_save(flags); - prm_write_reg(0xffff, OMAP24XX_PRCM_VOLTSETUP); + __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); curr_perf_level = level; local_irq_restore(flags); diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 996888526a5..0dc5952ab16 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -203,10 +203,10 @@ static void pm_init_serial_console(void) regs[reg_count++].val = cm_read_mod_reg(mod, reg) #define DUMP_PRM_REG(reg) \ regs[reg_count].name = #reg; \ - regs[reg_count++].val = prm_read_reg(reg) + regs[reg_count++].val = __raw_readl(reg) #define DUMP_CM_REG(reg) \ regs[reg_count].name = #reg; \ - regs[reg_count++].val = cm_read_reg(reg) + regs[reg_count++].val = __raw_readl(reg) #define DUMP_INTC_REG(reg, off) \ regs[reg_count].name = #reg; \ regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off))) @@ -442,14 +442,14 @@ no_sleep: prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); /* MPU domain wake events */ - l = prm_read_reg(OMAP24XX_PRCM_IRQSTATUS_MPU); + l = __raw_readl(OMAP24XX_PRCM_IRQSTATUS_MPU); if (l & 0x01) - prm_write_reg(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU); + __raw_writel(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU); if (l & 0x20) - prm_write_reg(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU); + __raw_writel(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU); /* Mask future PRCM-to-MPU interrupts */ - prm_write_reg(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU); + __raw_writel(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU); } static int omap2_i2c_active(void) @@ -648,7 +648,7 @@ static void __init prcm_setup_regs(void) u32 l; /* Enable autoidle */ - prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG); + __raw_writel(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG); /* Set all domain wakeup dependencies */ prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP); @@ -752,11 +752,11 @@ static void __init prcm_setup_regs(void) /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk * stabilisation */ - prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP); + __raw_writel(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP); /* Configure automatic voltage transition */ - prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP); - prm_write_reg(OMAP24XX_AUTO_EXTVOLT | + __raw_writel(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP); + __raw_writel(OMAP24XX_AUTO_EXTVOLT | (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | OMAP24XX_MEMRETCTRL | (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | @@ -774,7 +774,7 @@ int __init omap2_pm_init(void) int error; printk(KERN_INFO "Power Management for OMAP2 initializing\n"); - l = prm_read_reg(OMAP24XX_PRCM_REVISION); + l = __raw_readl(OMAP24XX_PRCM_REVISION); printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); osc_ck = clk_get(NULL, "osc_ck"); diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index a5a4161b304..125d1e24131 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -101,29 +101,16 @@ #ifndef __ASSEMBLER__ -/* Power/reset management global register get/set */ - -static void __attribute__((unused)) prm_write_reg(u32 val, void __iomem *addr) -{ - pr_debug("prm_write_reg: writing 0x%0x to 0x%0x\n", val, (u32)addr); - - __raw_writel(val, addr); -} - -static u32 __attribute__((unused)) prm_read_reg(void __iomem *addr) -{ - return __raw_readl(addr); -} - /* Read-modify-write bits in a PRM register */ -static u32 __attribute__((unused)) prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *va) +static __inline__ u32 __attribute__((unused)) prm_rmw_reg_bits(u32 mask, + u32 bits, void __iomem *va) { u32 v; - v = prm_read_reg(va); + v = __raw_readl(va); v &= ~mask; v |= bits; - prm_write_reg(v, va); + __raw_writel(v, va); return v; } @@ -200,14 +187,16 @@ static u32 __attribute__((unused)) prm_clear_mod_reg_bits(u32 bits, s16 module, /* Power/reset management domain register get/set */ -static void __attribute__((unused)) prm_write_mod_reg(u32 val, s16 module, s16 idx) +static __inline__ void __attribute__((unused)) prm_write_mod_reg(u32 val, + s16 module, s16 idx) { - prm_write_reg(val, OMAP_PRM_REGADDR(module, idx)); + __raw_writel(val, OMAP_PRM_REGADDR(module, idx)); } -static u32 __attribute__((unused)) prm_read_mod_reg(s16 module, s16 idx) +static __inline__ u32 __attribute__((unused)) prm_read_mod_reg(s16 module, + s16 idx) { - return prm_read_reg(OMAP_PRM_REGADDR(module, idx)); + return __raw_readl(OMAP_PRM_REGADDR(module, idx)); } #endif -- 2.41.1