From 6b6d79538c19b7746406c373fc2c555efff27b2e Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Jan 2008 01:20:07 -0700 Subject: [PATCH] 3430ES2 clock: separate 3430ES1/3430ES2 rates in clock code On the OMAP3430 architecture, some DPLL3 rates are only available on 3430ES2. We wish to avoid inadvertently selecting these on 3430ES1. So we need some way to mark these rates as being 3430ES2-only. To do so, add new rate flag RATE_IN_3430ES2, to be used for rates that only exist on 3430ES2. (I'm not aware of any 3430ES1-only rates, so, no corresponding 3430ES1 flag is currently defined.) RATE_IN_343X is still present and used for rates which exist on all 343X-level devices. The current code assumes that production rates will be identical to 3430ES2 rates, but this is easy enough to change if necessary. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock34xx.c | 7 +++-- arch/arm/mach-omap2/clock34xx.h | 44 ++++++++++++++++++++++++--- arch/arm/mach-omap2/cm_regbits_34xx.h | 3 +- include/asm-arm/arch-omap/clock.h | 12 +++++--- 4 files changed, 53 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index fd3b478db5c..2558a2392cb 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -177,10 +177,13 @@ int __init omap2_clk_init(void) * Update this if there are further clock changes between ES2 * and production parts */ - if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) + if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) { + /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ cpu_clkflg |= CLOCK_IN_OMAP3430ES1; - else + } else { + cpu_mask |= RATE_IN_3430ES2; cpu_clkflg |= CLOCK_IN_OMAP3430ES2; + } } clk_init(&omap2_clk_functions); diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index a822def9973..fd6388ab0d4 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -106,9 +106,8 @@ static const struct clksel_rate osc_sys_13m_rates[] = { { .div = 0 } }; -/* 3430ES2 only */ static const struct clksel_rate osc_sys_16_8m_rates[] = { - { .div = 1, .val = 5, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, { .div = 0 } }; @@ -308,8 +307,43 @@ static const struct clksel_rate div16_dpll_rates[] = { { .div = 0 } }; -static const struct clksel div2_dpll3m2_clksel[] = { - { .parent = &dpll3_ck, .rates = div2_rates }, +static const struct clksel_rate div31_dpll3_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, + { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, + { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, + { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, + { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, + { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, + { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, + { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, + { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, + { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, + { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, + { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, + { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, + { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, + { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, + { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, + { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, + { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, + { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, + { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, + { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, + { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, + { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, + { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, + { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, + { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, + { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, + { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, + { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, + { .div = 0 }, +}; + +static const struct clksel div31_dpll3m2_clksel[] = { + { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, { .parent = NULL } }; @@ -324,7 +358,7 @@ static struct clk dpll3_m2_ck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, - .clksel = div2_dpll3m2_clksel, + .clksel = div31_dpll3m2_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, .recalc = &omap2_clksel_recalc, diff --git a/arch/arm/mach-omap2/cm_regbits_34xx.h b/arch/arm/mach-omap2/cm_regbits_34xx.h index 65720e48462..e7cffa6d4d8 100644 --- a/arch/arm/mach-omap2/cm_regbits_34xx.h +++ b/arch/arm/mach-omap2/cm_regbits_34xx.h @@ -374,8 +374,9 @@ #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) /* CM_CLKSEL1_PLL */ +/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 -#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x3 << 27) +#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index 954638fee42..71893bb8a69 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -135,11 +135,13 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); #define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */ /* Clksel_rate flags */ -#define DEFAULT_RATE (1 << 0) -#define RATE_IN_242X (1 << 1) -#define RATE_IN_243X (1 << 2) -#define RATE_IN_343X (1 << 3) -#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) +#define DEFAULT_RATE (1 << 0) +#define RATE_IN_242X (1 << 1) +#define RATE_IN_243X (1 << 2) +#define RATE_IN_343X (1 << 3) /* rates common to all 343X */ +#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ + +#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ -- 2.41.1