From 4d03fa2c0f954cd0425101b183003f606c6dd4b1 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 9 Jun 2006 18:17:50 +0300 Subject: [PATCH] ARM: OMAP: omap_uwire: wait for tx complete before starting the next one The TDR register shouldn't be written when the CSRB flag is set. The fix solves the problem where one SPI transfer includes multiple 8 or 16 bit tx elements and the current transfer can be corrupted by accessing the TDR too early. Signed-off-by: Imre Deak Signed-off-by: Juha Yrjola --- drivers/spi/omap_uwire.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/spi/omap_uwire.c b/drivers/spi/omap_uwire.c index 3aa38904e0b..cc26c0d8a70 100644 --- a/drivers/spi/omap_uwire.c +++ b/drivers/spi/omap_uwire.c @@ -240,12 +240,13 @@ static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t) pr_debug("%s: write-%d =%04x\n", spi->dev.bus_id, bits, val); #endif + if (wait_uwire_csr_flag(CSRB, 0, 0)) + goto eio; + uwire_write_reg(UWIRE_TDR, val); /* start write */ val = START | w | (bits << 5); - if (wait_uwire_csr_flag(CSRB, 0, 0)) - goto eio; uwire_write_reg(UWIRE_CSR, val); len -= bytes; -- 2.41.1