From 3fc93030e5a792fdd0da3321487f5cbfd1143c2b Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 27 Jan 2009 11:29:39 +0200 Subject: [PATCH] ASoC: TWL4030: Syncronize the reg_cache for ANAMICL after the offset cancelation The offset cancelation bit in ANAMICL register is self cleanig. Make sure that the reg_cache holds the same value as the HW register. Signed-off-by: Peter Ujfalusi Signed-off-by: Mark Brown --- sound/soc/codecs/twl4030.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index 796f34cac85..24419afd319 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -913,6 +913,9 @@ static void twl4030_power_up(struct snd_soc_codec *codec) ((byte & TWL4030_CNCL_OFFSET_START) == TWL4030_CNCL_OFFSET_START)); + /* Make sure that the reg_cache has the same value as the HW */ + twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte); + /* anti-pop when changing analog gain */ regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1); twl4030_write(codec, TWL4030_REG_MISC_SET_1, -- 2.41.1