From 3a9e3a51dd47bd9e2fd6bcf3c893eb5729c6f1ee Mon Sep 17 00:00:00 2001 From: Tejun Heo <htejun@gmail.com> Date: Tue, 23 Oct 2007 15:27:31 +0900 Subject: [PATCH] jmicron: update quirk for JMB361/3/5/6 Set bits 0, 4, 5 and 7 of PCI configuration register 0x40 in the quirk. This has the following effects and is recommended by the vendor. * Force enable of IDE channels (used to be left alone as BIOS configured) * Change initial phase behavior of PIO cycle such that the host pulls down the bus instead of tristating it. Vendor recommends this setting. The above settings are better for the current generation of controllers and needed for the upcoming next generation. Tested on JMB363. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Ethan Hsiao <ethanhsiao@jmicron.com> Signed-off-by: Jeff Garzik <jeff@garzik.org> --- drivers/pci/quirks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 59d4da2734c..d0bb5b9d212 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -1230,7 +1230,7 @@ static void quirk_jmicron_ata(struct pci_dev *pdev) case PCI_DEVICE_ID_JMICRON_JMB363: /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ /* Set the class codes correctly and then direct IDE 0 */ - conf1 |= 0x00C2A102; /* Set 1, 8, 13, 15, 17, 22, 23 */ + conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ break; case PCI_DEVICE_ID_JMICRON_JMB368: -- 2.41.3