From 1ac64c8fa124e401daf020cabd9d0bf5b032e4ec Mon Sep 17 00:00:00 2001 From: Kalle Jokiniemi Date: Wed, 22 Oct 2008 09:47:06 +0300 Subject: [PATCH] OMAP3 DSS: Fixed FIFO buffer register field sizes The size status field in DISPC_[GFX | VID1 | VID2]_FIFO_SIZE_STATUS register is 11 bits wide in OMAP3, but only 9 bits were read. Similarly, the threshold field in DISPC_[GFX | VID1 | VID2]_FIFO_THRESHOLD register is 12 bits wide, while only 9 bits were written in it. This patch extends the bit field sizes used in setup_plane_fifo to correspond to ones in OMAP3. In OMAP2 the extra bits are reserved, so no harm should come from extending the bit fields. Signed-off-by: Kalle Jokiniemi Signed-off-by: Tony Lindgren --- drivers/video/omap/dispc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c index beda40b2376..c140c214223 100644 --- a/drivers/video/omap/dispc.c +++ b/drivers/video/omap/dispc.c @@ -290,7 +290,7 @@ static void setup_plane_fifo(int plane, int ext_mode) BUG_ON(plane > 2); l = dispc_read_reg(fsz_reg[plane]); - l &= FLD_MASK(0, 9); + l &= FLD_MASK(0, 11); if (ext_mode) { low = l * 3 / 4; high = l; @@ -298,7 +298,7 @@ static void setup_plane_fifo(int plane, int ext_mode) low = l / 4; high = l * 3 / 4; } - MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 9) | FLD_MASK(0, 9), + MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 12) | FLD_MASK(0, 12), (high << 16) | low); } -- 2.41.1