From 14ee306d7d5555c75a28e17dccdfbeda5729da17 Mon Sep 17 00:00:00 2001 From: Jarkko Lavinen Date: Tue, 28 Oct 2008 11:12:28 +0200 Subject: [PATCH] OMAP: HSMMC: Fix suspend/resume for MMCHS2 For HSMMC2 and HSMMC3 set SDVSS to 1.8V in HCTL before enabling the SDBP bit. Signed-off-by: Jarkko Lavinen --- drivers/mmc/host/omap_hsmmc.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index a134f76ede2..4bc25c0d51d 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -1197,15 +1197,16 @@ static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state) } if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) { - OMAP_HSMMC_WRITE(host->base, HCTL, - OMAP_HSMMC_READ(host->base, HCTL) - & SDVSCLR); - OMAP_HSMMC_WRITE(host->base, HCTL, - OMAP_HSMMC_READ(host->base, HCTL) - | SDVS30); - OMAP_HSMMC_WRITE(host->base, HCTL, - OMAP_HSMMC_READ(host->base, HCTL) - | SDBP); + u32 hctl = OMAP_HSMMC_READ(host->base, HCTL) & + SDVSCLR; + + if (host->id == OMAP_MMC1_DEVID) + hctl |= SDVS30; + else + hctl |= SDVS18; + + OMAP_HSMMC_WRITE(host->base, HCTL, hctl); + OMAP_HSMMC_WRITE(host->base, HCTL, hctl | SDBP); } mmc_omap_fclk_state(host, OFF); -- 2.41.1