[ARM] orion5x: update of FPGA ID's for the TS-78xx
Received official word finally from Technological Systems on which
FPGA ID's they have released unto the world. Also an additional of
a dummy entry matching the FPGA ID of the Verilog template on our
wiki.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
Eric Miao [Tue, 20 Jan 2009 06:15:18 +0000 (14:15 +0800)]
[ARM] pxa: add base support for Marvell's PXA168 processor line
"""The Marvell® PXA168 processor is the first in a family of application
processors targeted at mass market opportunities in computing and consumer
devices. It balances high computing and multimedia performance with low
power consumption to support extended battery life, and includes a wealth
of integrated peripherals to reduce overall BOM cost .... """
See http://www.marvell.com/featured/pxa168.jsp for more information.
1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core,
there are many enhancements like instructions for flushing the
whole D-cache, and so on
2. Clock reuses Russell's common clkdev, and added the basic support
for UART1/2.
3. Devices are a bit different from the 'mach-pxa' way, the platform
devices are now dynamically allocated only when necessary (i.e.
when pxa_register_device() is called). Description for each device
are stored in an array of 'struct pxa_device_desc'. Now that:
a. this array of device description is marked with __initdata and
can be freed up system is fully up
b. which means board code has to add all needed devices early in
his initializing function
c. platform specific data can now be marked as __initdata since
they are allocated and copied by platform_device_add_data()
4. only the basic UART1/2/3 are added, more devices will come later.
Signed-off-by: Jason Chagas <chagas@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
Eric Miao [Tue, 20 Jan 2009 04:09:06 +0000 (12:09 +0800)]
[ARM] pxa: move common GPIO handling code into plat-pxa
1. add common GPIO handling code into [arch/arm/plat-pxa]
2. common code in <mach/gpio.h> moved into <plat/gpio.h>, new processors
should implement its own <mach/gpio.h>, provide the following required
definitions and '#include <plat/gpio.h>' in the end:
- GPIO_REGS_VIRT for mapped virtual address of the GPIO registers'
physical I/O memory
- macros of GPLR(), GPSR(), GPDR() for constant optimization for
functions gpio_{set,get}_value() (so that bit-bang code can still
have tolerable performance)
- NR_BUILTIN_GPIO for the number of onchip GPIO
- definitions of __gpio_is_inverted() and __gpio_is_occupied(), they
can be either macros or inlined functions
Eric Miao [Tue, 20 Jan 2009 04:06:01 +0000 (12:06 +0800)]
[ARM] pxa: introduce plat-pxa for PXA common code and add DMA support
1. introduce folder of 'arch/arm/plat-pxa' for common code across different
PXA processor families
2. initially moved DMA code into plat-pxa
3. common code in <mach/dma.h> moved into <plat/dma.h>, new processors
should implement its own <mach/dma.h>, provide the following required
definitions and '#include <plat/dma.h>' in the end:
- DMAC_REGS_VIRT for mapped virtual address of the DMA registers'
physical I/O memory
Daniel Mack [Mon, 23 Mar 2009 01:04:18 +0000 (02:04 +0100)]
[ARM] pxa: Colibri PXA320 module basics
This adds basic support for Colibri PXA320 modules.
The file colibri-320.c only contains settings specific to this module,
such as the Ethernet interface.
Cc: Matthias Meier <matthias.j.meier@gmx.net> Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Eric Miao <eric.miao@marvell.com>
Daniel Mack [Mon, 23 Mar 2009 01:04:17 +0000 (02:04 +0100)]
[ARM] pxa: Refactor Colibri board support code
- Move common function for all Colibri PXA3xx boards to the newly
added colibri-pxa3xx.c
- Drop some unnecessary defines from colibri.h
- Make Kconfig reflect the fact that code for colibri 300 module does
also work for the 310 model
- Give up on the huge pin config table which was messed up with lots of
#ifdefs and switch over to locally defined tables for configured
functions
Cc: Matthias Meier <matthias.j.meier@gmx.net> Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Eric Miao <eric.miao@marvell.com>
Russell King [Thu, 19 Mar 2009 16:20:24 +0000 (16:20 +0000)]
[ARM] pass reboot command line to arch_reset()
OMAP wishes to pass state to the boot loader upon reboot in order to
instruct it whether to wait for USB-based reflashing or not. There is
already a facility to do this via the reboot() syscall, except we ignore
the string passed to machine_restart().
This patch fixes things to pass this string to arch_reset(). This means
that we keep the reboot mode limited to telling the kernel _how_ to
perform the reboot which should be independent of what we request the
boot loader to do.
Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] pxa: make second argument of clk_add_alias a name instead of the device
clk_add_alias is commonly called for platform devices that are not yet
registered in the device tree. Thus the clock alias is associated with
NULL device name. Fix this by passing the device name instead of just
device pointer.
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
Nicolas Pitre [Fri, 19 Sep 2008 04:36:12 +0000 (00:36 -0400)]
[ARM] add CONFIG_HIGHMEM option
Here it is... HIGHMEM for the ARM architecture. :-)
If you don't have enough ram for highmem pages to be allocated and still
want to test this, then the cmdline option "vmalloc=" can be used with
a value large enough to force the highmem threshold down.
Successfully tested on a Marvell DB-78x00-BP Development Board with
2 GB of RAM.
Nicolas Pitre [Tue, 4 Nov 2008 05:48:42 +0000 (00:48 -0500)]
[ARM] ignore high memory with VIPT aliasing caches
VIPT aliasing caches have issues of their own which are not yet handled.
Usage of discard_old_kernel_data() in copypage-v6.c is not highmem ready,
kmap/fixmap stuff doesn't take account of cache colouring, etc.
If/when those issues are handled then this could be reverted.
Nicolas Pitre [Fri, 19 Sep 2008 02:55:47 +0000 (22:55 -0400)]
[ARM] xsc3: add highmem support to L2 cache handling code
On xsc3, L2 cache ops are possible only on virtual addresses. The code
is rearranged so to have a linear progression requiring the least amount
of pte setups in the highmem case. To protect the virtual mapping so
created, interrupts must be disabled currently up to a page worth of
address range.
The interrupt disabling is done in a way to minimize the overhead within
the inner loop. The alternative would consist in separate code for
the highmem and non highmem compilation which is less preferable.
Nicolas Pitre [Fri, 12 Sep 2008 20:11:51 +0000 (16:11 -0400)]
[ARM] Feroceon: add highmem support to L2 cache handling code
The choice is between looping over the physical range and performing
single cache line operations, or to map highmem pages somewhere, as
cache range ops are possible only on virtual addresses.
Because L2 range ops are much faster, we go with the later by factoring
the physical-to-virtual address conversion and use a fixmap entry for it
in the HIGHMEM case.
Possible future optimizations to avoid the pte setup cost:
- do the pte setup for highmem pages only
- determine a threshold for doing a line-by-line processing on physical
addresses when the range is small
Nicolas Pitre [Tue, 9 Sep 2008 19:54:13 +0000 (15:54 -0400)]
[ARM] make page_to_dma() highmem aware
If a machine class has a custom __virt_to_bus() implementation then it
must provide a __arch_page_to_dma() implementation as well which is
_not_ based on page_address() to support highmem.
This patch fixes existing __arch_page_to_dma() and provide a default
implementation otherwise. The default implementation for highmem is
based on __pfn_to_bus() which is defined only when no custom
__virt_to_bus() is provided by the machine class.
That leaves only ebsa110 and footbridge which cannot support highmem
until they provide their own __arch_page_to_dma() implementation.
But highmem support on those legacy platforms with limited memory is
certainly not a priority.
Nicolas Pitre [Fri, 13 Mar 2009 02:52:09 +0000 (22:52 -0400)]
[ARM] introduce dma_cache_maint_page()
This is a helper to be used by the DMA mapping API to handle cache
maintenance for memory identified by a page structure instead of a
virtual address. Those pages may or may not be highmem pages, and
when they're highmem pages, they may or may not be virtually mapped.
When they're not mapped then there is no L1 cache to worry about. But
even in that case the L2 cache must be processed since unmapped highmem
pages can still be L2 cached.
Nicolas Pitre [Thu, 5 Mar 2009 03:49:41 +0000 (22:49 -0500)]
highmem: atomic highmem kmap page pinning
Most ARM machines have a non IO coherent cache, meaning that the
dma_map_*() set of functions must clean and/or invalidate the affected
memory manually before DMA occurs. And because the majority of those
machines have a VIVT cache, the cache maintenance operations must be
performed using virtual
addresses.
When a highmem page is kunmap'd, its mapping (and cache) remains in place
in case it is kmap'd again. However if dma_map_page() is then called with
such a page, some cache maintenance on the remaining mapping must be
performed. In that case, page_address(page) is non null and we can use
that to synchronize the cache.
It is unlikely but still possible for kmap() to race and recycle the
virtual address obtained above, and use it for another page before some
on-going cache invalidation loop in dma_map_page() is done. In that case,
the new mapping could end up with dirty cache lines for another page,
and the unsuspecting cache invalidation loop in dma_map_page() might
simply discard those dirty cache lines resulting in data loss.
For example, let's consider this sequence of events:
- dma_map_page(..., DMA_FROM_DEVICE) is called on a highmem page.
--> - vaddr = page_address(page) is non null. In this case
it is likely that the page has valid cache lines
associated with vaddr. Remember that the cache is VIVT.
--> for (i = vaddr; i < vaddr + PAGE_SIZE; i += 32)
invalidate_cache_line(i);
*** preemption occurs in the middle of the loop above ***
- kmap_high() is called for a different page.
--> - last_pkmap_nr wraps to zero and flush_all_zero_pkmaps()
is called. The pkmap_count value for the page passed
to dma_map_page() above happens to be 1, so the page
is unmapped. But prior to that, flush_cache_kmaps()
cleared the cache for it. So far so good.
- A fresh pkmap entry is assigned for this kmap request.
The Murphy law says this pkmap entry will eventually
happen to use the same vaddr as the one which used to
belong to the other page being processed by
dma_map_page() in the preempted thread above.
- The kmap_high() caller start dirtying the cache using the
just assigned virtual mapping for its page.
*** the first thread is rescheduled ***
- The for(...) loop is resumed, but now cached
data belonging to a different physical page is
being discarded !
And this is not only a preemption issue as ARM can be SMP as well,
making the above scenario just as likely. Hence the need for some kind
of pkmap page pinning which can be used in any context, primarily for
the benefit of dma_map_page() on ARM.
This provides the necessary interface to cope with the above issue if
ARCH_NEEDS_KMAP_HIGH_GET is defined, otherwise the resulting code is
unchanged.
Signed-off-by: Nicolas Pitre <nico@marvell.com> Reviewed-by: MinChan Kim <minchan.kim@gmail.com> Acked-by: Andrew Morton <akpm@linux-foundation.org>
Nicolas Pitre [Mon, 15 Sep 2008 20:44:55 +0000 (16:44 -0400)]
[ARM] kmap support
The kmap virtual area borrows a 2MB range at the top of the 16MB area
below PAGE_OFFSET currently reserved for kernel modules and/or the
XIP kernel. This 2MB corresponds to the range covered by 2 consecutive
second-level page tables, or a single pmd entry as seen by the Linux
page table abstraction. Because XIP kernels are unlikely to be seen
on systems needing highmem support, there shouldn't be any shortage of
VM space for modules (14 MB for modules is still way more than twice the
typical usage).
Because the virtual mapping of highmem pages can go away at any moment
after kunmap() is called on them, we need to bypass the delayed cache
flushing provided by flush_dcache_page() in that case.
The atomic kmap versions are based on fixmaps, and
__cpuc_flush_dcache_page() is used directly in that case.
Nicolas Pitre [Tue, 16 Sep 2008 17:05:53 +0000 (13:05 -0400)]
[ARM] fixmap support
This is the minimum fixmap interface expected to be implemented by
architectures supporting highmem.
We have a second level page table already allocated and covering
0xfff00000-0xffffffff because the exception vector page is located
at 0xffff0000, and various cache tricks already use some entries above
0xffff0000. Therefore the PTEs covering 0xfff00000-0xfffeffff are free
to be used.
However the XScale cache flushing code already uses virtual addresses
between 0xfffe0000 and 0xfffeffff.
So this reserves the 0xfff00000-0xfffdffff range for fixmap stuff.
The Documentation/arm/memory.txt information is updated accordingly,
including the information about the actual top of DMA memory mapping
region which didn't match the code.
Dmitry Artamonow [Sun, 15 Mar 2009 18:09:50 +0000 (19:09 +0100)]
[ARM] 5424/1: h3600: clean up mtd partitions table
Right now iPaq h3600's default MTD partitions table is a mess. It has
two #ifdefs with #else, giving total 3 variants, depending on your
kernel config. Replace all this with simple two-partitions scheme
(bootloader + rootfs), that used by both shipped WindowsCE and
most of the linux distributions (Familiar, Angstrom)
Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Ilya Yanok [Wed, 11 Mar 2009 00:22:00 +0000 (03:22 +0300)]
qong: basic support for Dave/DENX QongEVB-LITE board
This patch adds basic support for Dave/DENX QongEVB-LITE i.MX31-based
board. It includes support for clocks initialization, UART1, NOR-flash,
FPGA-attached NAND flash and DNET ethernet controller (inside FPGA).
Sascha Hauer [Fri, 6 Feb 2009 16:48:59 +0000 (17:48 +0100)]
[ARM] MX35: add clock support
This patch adds clock support for i.MX35 SoCs. We do not support setting
of clock rates yet, but most interesting clock rates should be reported.
I couldn't test all clock rates and the datasheet contains some obvious
bugs, so expect some bugs in this code.
Sascha Hauer [Fri, 6 Feb 2009 14:38:22 +0000 (15:38 +0100)]
[ARM] MXC: add cpu_is_ macros
We had hardcoded cpu_is_ macros for mxc architectures till now. As we
want to run the same kernel on i.MX31 and i.MX35 this patch adds cpu_is_
macros which expand to 0 or 1 if only one architecture is compiled in and
only check for the cpu type if more than one architecture is compiled
in.
Sascha Hauer [Mon, 2 Feb 2009 13:11:54 +0000 (14:11 +0100)]
[ARM] MX35: Add register definitions for the i.MX35
This patch moves the stuff common to i.MX31 and i.MX35 to mx3x.h and the
specifics to mx31.h/mx35.h. We can build a kernel which runs on i.MX31 and
i.MX35, so always include mx31.h and mx35.h
mx31moboard: initial support for various baseboards
This enables our mx31moboard to be used on the different baseboards that
we are developping according to the application needs. There are not
many differences between the boards for now, but when other peripherals
are available for mx31 the differences are going to grow.
projects / linux-2.6-omap-h63xx.git / log