From: Ralf Baechle Date: Fri, 6 Jul 2007 13:40:05 +0000 (+0100) Subject: [MIPS] Add macros to encode processor revisions. X-Git-Tag: v2.6.22~12^2~1 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=fde97822a295da9dffa4af643b49a58ffc4516ad;p=linux-2.6-omap-h63xx.git [MIPS] Add macros to encode processor revisions. Older processors used to encode processor version and revision in two 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores have switched to use the 8-bits as 3:3:2 bitfield with the last field as the patch number. Signed-off-by: Ralf Baechle --- diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index d38fdbf845b..2924069075e 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -124,6 +124,17 @@ #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 +/* + * Older processors used to encode processor version and revision in two + * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores + * have switched to use the 8-bits as 3:3:2 bitfield with the last field as + * the patch number. *ARGH* + */ +#define PRID_REV_ENCODE_44(ver, rev) \ + ((ver) << 4 | (rev)) +#define PRID_REV_ENCODE_332(ver, rev, patch) \ + ((ver) << 5 | (rev) << 2 | (patch)) + /* * FPU implementation/revision register (CP1 control register 0). *