From: Xu, Anthony <anthony.xu@intel.com>
Date: Mon, 9 Jan 2006 02:36:35 +0000 (+0800)
Subject: [IA64] pal cache flush patch
X-Git-Tag: v2.6.16-rc1~82^2~2
X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=f15ac5801fdc1b217c3b8b5dbc63a09371d2ee4d;p=linux-2.6-omap-h63xx.git

[IA64] pal cache flush patch

Because PAL spec has changed since 2002, you can goto
http://developer.intel.com/design/itanium/manuals/iiasdmanual.htm to
download new SDM, all PAL calls should be invoked with psr.ic=1, and
it's caller's responsibility to handle possible tlb miss.
Ia64_pal_cache_flush was written according to old spec, it is obsolete,
and this patch has ia64_pal_cache_flush conform to new spec.

Signed-off-by Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
---

diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index e828377ad29..7708ec669a3 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -927,7 +927,7 @@ static inline s64
 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
 {
 	struct ia64_pal_retval iprv;
-	PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
+	PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
 	if (vector)
 		*vector = iprv.v0;
 	*progress = iprv.v1;