From: David Daney <ddaney@caviumnetworks.com>
Date: Thu, 11 Dec 2008 23:33:35 +0000 (-0800)
Subject: MIPS: Add Cavium OCTEON slot into proper tlb category.
X-Git-Tag: v2.6.29-rc2~104^2~18
X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=ec454d8c4fee3b2feb87e594d806c0987c5dd538;p=linux-2.6-omap-h63xx.git

MIPS: Add Cavium OCTEON slot into proper tlb category.

Expand the case statement for build_tlb_write_entry so that it does
the right thing on Cavium CPU variants.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 979cf919728..42942038d0f 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -317,6 +317,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
 	case CPU_BCM3302:
 	case CPU_BCM4710:
 	case CPU_LOONGSON2:
+	case CPU_CAVIUM_OCTEON:
 		if (m4kc_tlbp_war())
 			uasm_i_nop(p);
 		tlbw(p);