From: Russell King Date: Tue, 20 Feb 2007 10:52:01 +0000 (+0000) Subject: [ARM] Merge remaining IOP code X-Git-Tag: v2.6.21-rc1~50^2~1 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=e80a0e6e7ccdf64575d4384cb4172860422f5b81;p=linux-2.6-omap-h63xx.git [ARM] Merge remaining IOP code Conflicts: include/asm-arm/arch-at91rm9200/entry-macro.S Signed-off-by: Russell King --- e80a0e6e7ccdf64575d4384cb4172860422f5b81 diff --cc include/asm-arm/arch-at91/entry-macro.S index 76c8cccf73a,00000000000..cc1d850a078 mode 100644,000000..100644 --- a/include/asm-arm/arch-at91/entry-macro.S +++ b/include/asm-arm/arch-at91/entry-macro.S @@@ -1,26 -1,0 +1,32 @@@ +/* + * include/asm-arm/arch-at91/entry-macro.S + * + * Copyright (C) 2003-2005 SAN People + * + * Low-level IRQ helper macros for AT91RM9200 platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include + + .macro disable_fiq + .endm + ++ .macro get_irqnr_preamble, base, tmp ++ .endm ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral + ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) + ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number + teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt + streq \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)] @ not going to be handled further, then ACK it now. + .endm + diff --cc include/asm-arm/arch-imx/entry-macro.S index 61bb0bdc1b1,d8cbafa6cc4..0b84e81031c --- a/include/asm-arm/arch-imx/entry-macro.S +++ b/include/asm-arm/arch-imx/entry-macro.S @@@ -11,15 -11,28 +11,22 @@@ .macro disable_fiq .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + #define AITC_NIVECSR 0x40 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, =IO_ADDRESS(IMX_AITC_BASE) + ldr \base, =IO_ADDRESS(IMX_AITC_BASE) @ Load offset & priority of the highest priority @ interrupt pending. - ldr \irqnr, [\irqstat, #AITC_NIVECSR] + ldr \irqstat, [\base, #AITC_NIVECSR] @ Shift off the priority leaving the offset or - @ "interrupt number" - mov \irqnr, \irqnr, lsr #16 - ldr \irqstat, =1 @ dummy compare - ldr \base, =0xFFFF // invalid interrupt - cmp \irqnr, \base - bne 1001f - ldr \irqstat, =0 -1001: - tst \irqstat, #1 @ to make the condition code = TRUE + @ "interrupt number", use arithmetic shift to + @ transform illegal source (0xffff) as -1 + mov \irqnr, \irqstat, asr #16 + adds \tmp, \irqnr, #1 .endm -