From: Mans Rullgard Date: Mon, 20 Oct 2008 23:24:23 +0000 (+0100) Subject: OMAP: Make dpll4_m4_ck programmable with clk_set_rate() X-Git-Tag: v2.6.28-omap1~88 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=e42218d45afbc3e654e289e021e6b80c657b16c2;p=linux-2.6-omap-h63xx.git OMAP: Make dpll4_m4_ck programmable with clk_set_rate() Filling the set_rate and round_rate fields of dpll4_m4_ck makes this clock programmable through clk_set_rate(). This is needed to give omapfb control over the dss1_alwon_fck rate. Signed-off-by: Mans Rullgard Acked-by: Paul Walmsley Signed-off-by: Tony Lindgren --- diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 0b95fcbb51f..1c2b49f3274 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -879,6 +879,8 @@ static struct clk dpll4_m6_ck = { PARENT_CONTROLS_CLOCK, .clkdm = { .name = "dpll4_clkdm" }, .recalc = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */