From: Andi Kleen Date: Wed, 30 Jan 2008 12:32:37 +0000 (+0100) Subject: x86: implement support to synchronize RDTSC through MFENCE on AMD CPUs X-Git-Tag: v2.6.25-rc1~1143^2~428 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=de4218634e3df6d73a3e6cdfdf3a17fa3bc7e013;p=linux-2.6-omap-h63xx.git x86: implement support to synchronize RDTSC through MFENCE on AMD CPUs According to AMD RDTSC can be synchronized through MFENCE. Implement the necessary CPUID bit for that. Cc: andreas.herrmann3@amd.com Signed-off-by: Andi Kleen Signed-off-by: Ingo Molnar Signed-off-by: Thomas Gleixner --- diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 1ff88c7f45c..aaa8101d3d8 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -301,6 +301,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) /* K6s reports MCEs but don't actually have all the MSRs */ if (c->x86 < 6) clear_bit(X86_FEATURE_MCE, c->x86_capability); + + if (cpu_has_xmm) + set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability); } static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size) diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c index 02409100f45..2139aa6ac46 100644 --- a/arch/x86/kernel/setup_64.c +++ b/arch/x86/kernel/setup_64.c @@ -746,8 +746,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11) set_cpu_cap(c, X86_FEATURE_K8); - /* RDTSC can be speculated around */ - clear_cpu_cap(c, X86_FEATURE_SYNC_RDTSC); + /* MFENCE stops RDTSC speculation */ + set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); /* Family 10 doesn't support C states in MWAIT so don't use it */ if (c->x86 == 0x10 && !force_mwait) diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h index 75e2f78a7fd..7d53eea8b94 100644 --- a/include/asm-x86/cpufeature.h +++ b/include/asm-x86/cpufeature.h @@ -79,6 +79,7 @@ /* 14 free */ #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ +#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */