From: H. Peter Anvin <hpa@zytor.com>
Date: Thu, 4 Sep 2008 16:21:21 +0000 (-0700)
Subject: Merge branch 'x86/cpu' into x86/x2apic
X-Git-Tag: v2.6.28-rc1~711^2^2~44^2~1^2
X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=aa3341a168883654d1b13f5931c5ed2762537831;p=linux-2.6-omap-h63xx.git

Merge branch 'x86/cpu' into x86/x2apic

Conflicts:

	arch/x86/kernel/cpu/feature_names.c
	include/asm-x86/cpufeature.h
---

aa3341a168883654d1b13f5931c5ed2762537831
diff --cc include/asm-x86/cpufeature.h
index c6845b94be8,24d99d65741..4f521c07d01
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@@ -74,39 -82,50 +82,51 @@@
  #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
  #define X86_FEATURE_PEBS	(3*32+12) /* Precise-Event Based Sampling */
  #define X86_FEATURE_BTS		(3*32+13) /* Branch Trace Store */
- #define X86_FEATURE_SYSCALL32	(3*32+14) /* syscall in ia32 userspace */
- #define X86_FEATURE_SYSENTER32	(3*32+15) /* sysenter in ia32 userspace */
- #define X86_FEATURE_REP_GOOD	(3*32+16) /* rep microcode works well on this CPU */
- #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
- #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
- #define X86_FEATURE_11AP	(3*32+19) /* Bad local APIC aka 11AP */
+ #define X86_FEATURE_SYSCALL32	(3*32+14) /* "" syscall in ia32 userspace */
+ #define X86_FEATURE_SYSENTER32	(3*32+15) /* "" sysenter in ia32 userspace */
+ #define X86_FEATURE_REP_GOOD	(3*32+16) /* rep microcode works well */
+ #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
+ #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
+ #define X86_FEATURE_11AP	(3*32+19) /* "" Bad local APIC aka 11AP */
  #define X86_FEATURE_NOPL	(3*32+20) /* The NOPL (0F 1F) instructions */
 +#define X86_FEATURE_XTOPOLOGY	(3*32+21) /* cpu topology enum extensions */
  
  /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
- #define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */
- #define X86_FEATURE_MWAIT	(4*32+ 3) /* Monitor/Mwait support */
- #define X86_FEATURE_DSCPL	(4*32+ 4) /* CPL Qualified Debug Store */
+ #define X86_FEATURE_XMM3	(4*32+ 0) /* "pni" SSE-3 */
+ #define X86_FEATURE_PCLMULQDQ	(4*32+ 1) /* PCLMULQDQ instruction */
+ #define X86_FEATURE_DTES64	(4*32+ 2) /* 64-bit Debug Store */
+ #define X86_FEATURE_MWAIT	(4*32+ 3) /* "monitor" Monitor/Mwait support */
+ #define X86_FEATURE_DSCPL	(4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
+ #define X86_FEATURE_VMX		(4*32+ 5) /* Hardware virtualization */
+ #define X86_FEATURE_SMX		(4*32+ 6) /* Safer mode */
  #define X86_FEATURE_EST		(4*32+ 7) /* Enhanced SpeedStep */
  #define X86_FEATURE_TM2		(4*32+ 8) /* Thermal Monitor 2 */
+ #define X86_FEATURE_SSSE3	(4*32+ 9) /* Supplemental SSE-3 */
  #define X86_FEATURE_CID		(4*32+10) /* Context ID */
+ #define X86_FEATURE_FMA		(4*32+12) /* Fused multiply-add */
  #define X86_FEATURE_CX16	(4*32+13) /* CMPXCHG16B */
  #define X86_FEATURE_XTPR	(4*32+14) /* Send Task Priority Messages */
+ #define X86_FEATURE_PDCM	(4*32+15) /* Performance Capabilities */
  #define X86_FEATURE_DCA		(4*32+18) /* Direct Cache Access */
- #define X86_FEATURE_XMM4_2	(4*32+20) /* Streaming SIMD Extensions-4.2 */
+ #define X86_FEATURE_XMM4_1	(4*32+19) /* "sse4_1" SSE-4.1 */
+ #define X86_FEATURE_XMM4_2	(4*32+20) /* "sse4_2" SSE-4.2 */
  #define X86_FEATURE_X2APIC	(4*32+21) /* x2APIC */
+ #define X86_FEATURE_AES		(4*32+25) /* AES instructions */
+ #define X86_FEATURE_XSAVE	(4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
+ #define X86_FEATURE_OSXSAVE	(4*32+27) /* "" XSAVE enabled in the OS */
+ #define X86_FEATURE_AVX		(4*32+28) /* Advanced Vector Extensions */
  
  /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
- #define X86_FEATURE_XSTORE	(5*32+ 2) /* on-CPU RNG present (xstore insn) */
- #define X86_FEATURE_XSTORE_EN	(5*32+ 3) /* on-CPU RNG enabled */
- #define X86_FEATURE_XCRYPT	(5*32+ 6) /* on-CPU crypto (xcrypt insn) */
- #define X86_FEATURE_XCRYPT_EN	(5*32+ 7) /* on-CPU crypto enabled */
+ #define X86_FEATURE_XSTORE	(5*32+ 2) /* "rng" RNG present (xstore) */
+ #define X86_FEATURE_XSTORE_EN	(5*32+ 3) /* "rng_en" RNG enabled */
+ #define X86_FEATURE_XCRYPT	(5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
+ #define X86_FEATURE_XCRYPT_EN	(5*32+ 7) /* "ace_en" on-CPU crypto enabled */
  #define X86_FEATURE_ACE2	(5*32+ 8) /* Advanced Cryptography Engine v2 */
  #define X86_FEATURE_ACE2_EN	(5*32+ 9) /* ACE v2 enabled */
- #define X86_FEATURE_PHE		(5*32+ 10) /* PadLock Hash Engine */
- #define X86_FEATURE_PHE_EN	(5*32+ 11) /* PHE enabled */
- #define X86_FEATURE_PMM		(5*32+ 12) /* PadLock Montgomery Multiplier */
- #define X86_FEATURE_PMM_EN	(5*32+ 13) /* PMM enabled */
+ #define X86_FEATURE_PHE		(5*32+10) /* PadLock Hash Engine */
+ #define X86_FEATURE_PHE_EN	(5*32+11) /* PHE enabled */
+ #define X86_FEATURE_PMM		(5*32+12) /* PadLock Montgomery Multiplier */
+ #define X86_FEATURE_PMM_EN	(5*32+13) /* PMM enabled */
  
  /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
  #define X86_FEATURE_LAHF_LM	(6*32+ 0) /* LAHF/SAHF in long mode */