From: Karsten Wiese Date: Sat, 3 Sep 2005 22:56:33 +0000 (-0700) Subject: [PATCH] via vt8237 apic bypass deassertion quirk X-Git-Tag: v2.6.14-rc1~860 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=a1740913cae231fb8e485306fb09671ed9a6e550;p=linux-2.6-omap-h63xx.git [PATCH] via vt8237 apic bypass deassertion quirk The VIA VT8237's IOAPIC sends 'APIC De-Assert Messages' by default, causing another CPU interrupt when the IRQ pin is de-asserted. This feature is switched off by the patch to get rid of doubled ioapic level interrupt rates. Signed-off-by: Karsten Wiese Tested-by: Ingo Molnar Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index bb36bb69803..140354a2aa7 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -421,6 +421,25 @@ static void __devinit quirk_via_ioapic(struct pci_dev *dev) } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); +/* + * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. + * This leads to doubled level interrupt rates. + * Set this bit to get rid of cycle wastage. + * Otherwise uncritical. + */ +static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) +{ + u8 misc_control2; +#define BYPASS_APIC_DEASSERT 8 + + pci_read_config_byte(dev, 0x5B, &misc_control2); + if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { + printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); + pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); + /* * The AMD io apic can hang the box when an apic irq is masked. * We check all revs >= B0 (yet not in the pre production!) as the bug