From: Vitaly Wool Date: Sat, 12 Jan 2008 13:03:40 +0000 (+0300) Subject: [MIPS] pnx8xxx: clocksource cleanups X-Git-Tag: v2.6.25-rc1~1163^2~21 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=9900485893c004245cbaeef050fe6ba5453a5925;p=linux-2.6-omap-h63xx.git [MIPS] pnx8xxx: clocksource cleanups Signed-off-by: Vitaly Wool Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c index 6d494e0de3d..62f495b57f9 100644 --- a/arch/mips/philips/pnx8550/common/time.c +++ b/arch/mips/philips/pnx8550/common/time.c @@ -47,11 +47,6 @@ static struct clocksource pnx_clocksource = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -static void timer_ack(void) -{ - write_c0_compare(cpj); -} - static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *c = dev_id; @@ -94,30 +89,22 @@ static struct clock_event_device pnx8xxx_clockevent = { .set_next_event = pnx8xxx_set_next_event, }; -/* - * plat_time_init() - it does the following things: - * - * 1) plat_time_init() - - * a) (optional) set up RTC routines, - * b) (optional) calibrate and set the mips_hpt_frequency - * (only needed if you intended to use cpu counter as timer interrupt - * source) - */ +static inline void timer_ack(void) +{ + write_c0_compare(cpj); +} __init void plat_time_init(void) { - unsigned int configPR; - unsigned int n; - unsigned int m; - unsigned int p; - unsigned int pow2p; + unsigned int configPR; + unsigned int n; + unsigned int m; + unsigned int p; + unsigned int pow2p; clockevents_register_device(&pnx8xxx_clockevent); clocksource_register(&pnx_clocksource); - setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq); - setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); - /* Timer 1 start */ configPR = read_c0_config7(); configPR &= ~0x00000008; @@ -158,6 +145,6 @@ __init void plat_time_init(void) write_c0_count2(0); write_c0_compare2(0xffffffff); + setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq); + setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); } - -