From: Paul Walmsley Date: Thu, 27 Sep 2007 06:11:21 +0000 (-0600) Subject: omap2 clock: split out OMAP2/3 common defines, clksel rates X-Git-Tag: v2.6.23-omap1~57 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=926865d2354fbada3c07a66f80b45309188cceb5;p=linux-2.6-omap-h63xx.git omap2 clock: split out OMAP2/3 common defines, clksel rates This patch is a collection of minor clock code changes in preparation for the OMAP3 clock merge. Specifically: * Since general-purpose timer and GFX module L3 clksel rates are common to OMAP2/3, hoist those into asm/arch/clock.h. * Since the CM_FCLKEN define is common to OMAP2/3, remove the OMAP24XX_ prefix. * Designate the clock transaction code in clock.c as being OMAP2-specific. * Fix a potential null pointer dereference that could occur when debugging is enabled in omap2_init_clksel_parent(). Clocks with no initially-defined parent (as is possible for clksel clocks) will trigger an oops due to a buggy conditional. * Clean up omap2_wait_clock_ready(). * Remove unused struct dpll_params auto_idle* fields. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 7c18a14f5ee..0fba409e089 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -19,6 +19,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#undef DEBUG + #include #include #include @@ -31,6 +33,7 @@ #include #include +#include #include #include "memory.h" @@ -41,9 +44,7 @@ #include "cm.h" #include "cm_regbits_24xx.h" -#undef DEBUG - -#define MAX_PLL_LOCK_WAIT 100000 +#define MAX_CLOCK_ENABLE_WAIT 100000 u8 cpu_mask; @@ -84,7 +85,7 @@ void omap2_init_clksel_parent(struct clk *clk) pr_debug("clock: inited %s parent " "to %s (was %s)\n", clk->name, clks->parent->name, - ((clk->parent->name) ? + ((clk->parent) ? clk->parent->name : "NULL")); clk->parent = clks->parent; }; @@ -138,10 +139,14 @@ void omap2_fixed_divisor_recalc(struct clk *clk) propagate_rate(clk); } -/* - * omap2_wait_clock_ready - wait for PLL to lock +/** + * omap2_wait_clock_ready - wait for clock to enable + * @reg: physical address of clock IDLEST register + * @cval: value to test against to determine if the clock is active + * @name: name of the clock (for printk) * - * Returns 1 if the PLL locked, 0 if it failed to lock. + * Returns 1 if the clock enabled in time, or 0 if it failed to enable + * in roughly MAX_CLOCK_ENABLE_WAIT microseconds. */ int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name) { @@ -151,17 +156,17 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name) while (!(cm_read_reg(reg) & cval)) { ++i; udelay(1); - if (i == MAX_PLL_LOCK_WAIT) { - printk(KERN_ERR "Clock %s didn't lock in %d tries\n", - name, MAX_PLL_LOCK_WAIT); + if (i == MAX_CLOCK_ENABLE_WAIT) { + printk(KERN_ERR "Clock %s didn't enable in %d tries\n", + name, MAX_CLOCK_ENABLE_WAIT); break; } } - if (i) + if (i < MAX_CLOCK_ENABLE_WAIT) pr_debug("Clock %s stable after %d loops\n", name, i); - return (i < MAX_PLL_LOCK_WAIT) ? 1 : 0; + return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0; }; @@ -180,8 +185,9 @@ static void omap2_clk_wait_ready(struct clk *clk) else return; + /* REVISIT: What are the appropriate exclusions for 34XX? */ /* No check for DSS or cam clocks */ - if (((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */ + if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */ if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT || clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT || clk->enable_bit == OMAP24XX_EN_CAM_SHIFT) @@ -574,7 +580,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) clk->rate = clk->parent->rate / new_div; - if (clk->flags & DELAYED_APP) { + if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { prm_write_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); wmb(); } @@ -670,7 +676,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) __raw_writel(reg_val, src_addr); wmb(); - if (clk->flags & DELAYED_APP) { + if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { prm_write_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); wmb(); diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index a1e28ca730a..e14446dd01d 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -21,6 +21,8 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H #define __ARCH_ARM_MACH_OMAP2_CLOCK_H +#include + int omap2_clk_enable(struct clk *clk); void omap2_clk_disable(struct clk *clk); long omap2_clk_round_rate(struct clk *clk, unsigned long rate); @@ -49,4 +51,24 @@ u8 mask_to_shift(u32 mask); extern u8 cpu_mask; +/* clksel_rate data common to 24xx/343x */ +static const struct clksel_rate gpt_32k_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate gpt_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate gfx_l3_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, + { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X }, + { .div = 0 } +}; + + #endif diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index b792589e88e..96228948721 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -15,6 +15,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#undef DEBUG + #include #include #include @@ -37,8 +39,6 @@ #include "cm.h" #include "cm_regbits_24xx.h" -#undef DEBUG - /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ #define EN_APLL_STOPPED 0 #define EN_APLL_LOCKED 3 @@ -476,7 +476,8 @@ int __init omap2_clk_init(void) omap2_osc_clk_recalc(&osc_ck); - for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks); + for (clkp = onchip_24xx_clks; + clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); clkp++) { if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index d0c406d7f59..fe3f1892a2c 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -608,8 +608,6 @@ static const struct dpll_data dpll_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .mult_mask = OMAP24XX_DPLL_MULT_MASK, .div1_mask = OMAP24XX_DPLL_DIV_MASK, - .auto_idle_mask = OMAP24XX_AUTO_DPLL_MASK, - .auto_idle_val = 0x3, /* stop DPLL upon idle */ }; static struct clk dpll_ck = { @@ -965,7 +963,7 @@ static struct clk iva2_1_fck = { .parent = &core_ck, .flags = CLOCK_IN_OMAP243X | DELAYED_APP | RATE_PROPAGATES | CONFIG_PARTICIPANT, - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN), + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, @@ -1027,7 +1025,7 @@ static struct clk dsp_fck = { .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN), + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, @@ -1082,7 +1080,7 @@ static struct clk iva1_ifck = { .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP, - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN), + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, @@ -1097,7 +1095,7 @@ static struct clk iva1_mpu_int_ifck = { .name = "iva1_mpu_int_ifck", .parent = &iva1_ifck, .flags = CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN), + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, .fixed_div = 2, .recalc = &omap2_fixed_divisor_recalc, @@ -1232,20 +1230,9 @@ static struct clk ssi_ssr_sst_fck = { */ /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */ -/* - * These clksel_rate/clksel structs are shared between gfx_3d_fck and - * gfx_2d_fck - */ -static const struct clksel_rate gfx_fck_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, - { .div = 3, .val = 3, .flags = RATE_IN_243X }, - { .div = 4, .val = 4, .flags = RATE_IN_243X }, - { .div = 0 } -}; - +/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ static const struct clksel gfx_fck_clksel[] = { - { .parent = &core_l3_ck, .rates = gfx_fck_core_l3_rates }, + { .parent = &core_l3_ck, .rates = gfx_l3_rates }, { .parent = NULL }, }; @@ -1253,7 +1240,7 @@ static struct clk gfx_3d_fck = { .name = "gfx_3d_fck", .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN), + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_3D_SHIFT, .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_mask = OMAP_CLKSEL_GFX_MASK, @@ -1267,7 +1254,7 @@ static struct clk gfx_2d_fck = { .name = "gfx_2d_fck", .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN), + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_2D_SHIFT, .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_mask = OMAP_CLKSEL_GFX_MASK, @@ -1324,7 +1311,7 @@ static struct clk mdm_osc_ck = { .name = "mdm_osc_ck", .parent = &osc_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN), + .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), .enable_bit = OMAP2430_EN_OSC_SHIFT, .recalc = &followparent_recalc, }; @@ -1474,22 +1461,12 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */ * here will likely have an L4 interface parent, and may have multiple * functional clock parents. */ -static const struct clksel_rate gpt_32k_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate gpt_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, - { .div = 0 } -}; - static const struct clksel_rate gpt_alt_rates[] = { { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, { .div = 0 } }; -static const struct clksel gpt_clksel[] = { +static const struct clksel omap24xx_gpt_clksel[] = { { .parent = &func_32k_ck, .rates = gpt_32k_rates }, { .parent = &sys_ck, .rates = gpt_sys_rates }, { .parent = &alt_ck, .rates = gpt_alt_rates }, @@ -1509,12 +1486,12 @@ static struct clk gpt1_fck = { .name = "gpt1_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN), + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_GPT1_SHIFT, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, - .clksel = gpt_clksel, + .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate @@ -1538,7 +1515,7 @@ static struct clk gpt2_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, - .clksel = gpt_clksel, + .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, }; @@ -1560,7 +1537,7 @@ static struct clk gpt3_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, - .clksel = gpt_clksel, + .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, }; @@ -1582,7 +1559,7 @@ static struct clk gpt4_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, - .clksel = gpt_clksel, + .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, }; @@ -1604,7 +1581,7 @@ static struct clk gpt5_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, - .clksel = gpt_clksel, + .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, }; @@ -1626,7 +1603,7 @@ static struct clk gpt6_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, - .clksel = gpt_clksel, + .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, }; @@ -1648,7 +1625,7 @@ static struct clk gpt7_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, - .clksel = gpt_clksel, + .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, }; @@ -1670,7 +1647,7 @@ static struct clk gpt8_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, - .clksel = gpt_clksel, + .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, }; @@ -1692,7 +1669,7 @@ static struct clk gpt9_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, - .clksel = gpt_clksel, + .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, }; @@ -1714,7 +1691,7 @@ static struct clk gpt10_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, - .clksel = gpt_clksel, + .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, }; @@ -1736,7 +1713,7 @@ static struct clk gpt11_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, - .clksel = gpt_clksel, + .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, }; @@ -1758,7 +1735,7 @@ static struct clk gpt12_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, - .clksel = gpt_clksel, + .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, }; @@ -1979,7 +1956,7 @@ static struct clk gpios_fck = { .name = "gpios_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN), + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, .recalc = &followparent_recalc, }; @@ -1997,7 +1974,7 @@ static struct clk mpu_wdt_fck = { .name = "mpu_wdt_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN), + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, .recalc = &followparent_recalc, }; @@ -2495,7 +2472,7 @@ static struct clk virt_prcm_set = { .round_rate = &omap2_round_to_table_rate, }; -static struct clk *onchip_clks[] __initdata = { +static struct clk *onchip_24xx_clks[] __initdata = { /* external root sources */ &func_32k_ck, &osc_ck, diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index d7d7682ed4e..a6f91f1ec05 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -54,6 +54,7 @@ static u32 __attribute__((unused)) cm_read_reg(void __iomem *addr) /* Common between 24xx and 34xx */ #define CM_FCLKEN1 0x0000 +#define CM_FCLKEN CM_FCLKEN1 #define CM_CLKEN CM_FCLKEN1 #define CM_ICLKEN1 0x0010 #define CM_ICLKEN CM_ICLKEN1 @@ -72,7 +73,6 @@ static u32 __attribute__((unused)) cm_read_reg(void __iomem *addr) /* Architecture-specific registers */ -#define OMAP24XX_CM_FCLKEN CM_FCLKEN1 #define OMAP24XX_CM_FCLKEN2 0x0004 #define OMAP24XX_CM_ICLKEN4 0x001c #define OMAP24XX_CM_AUTOIDLE3 0x0038 diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index 827a93f7e99..2e471c51e09 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -33,8 +33,6 @@ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; - u32 auto_idle_mask; - u8 auto_idle_val; }; #endif