From: Dirk Behme <dirk.behme@googlemail.com>
Date: Sun, 11 May 2008 06:12:48 +0000 (+0200)
Subject: ARM: OMAP3: Check for L2 cache enabled
X-Git-Tag: v2.6.26-omap1~123^2~105
X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=74c89552b4a5f9b5b066f74fa265248f9b5d3f1d;p=linux-2.6-omap-h63xx.git

ARM: OMAP3: Check for L2 cache enabled

Enabling L2 cache of Cortex-A8 based OMAP3 has to be done by
bootloader. Check if this is done and warn if not.

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Acked-by: Felipe Balbi <felipe.balbi@nokia.com>

----

Changes in v3: Remove braces. Thanks to Felipe for review!
Signed-off-by: Tony Lindgren <tony@atomide.com>
---

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 835452b43a7..0db34ba86ef 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -267,3 +267,25 @@ void __init omap2_check_revision(void)
 
 }
 
+#ifdef CONFIG_ARCH_OMAP3
+/*
+ * OMAP3 has L2 cache which has to be enabled by bootloader.
+ */
+static int __init omap3_check_l2cache(void)
+{
+	u32 val;
+
+	/* Get CP15 AUX register, bit 1 enabled indicates L2 cache is on */
+	asm volatile("mrc p15, 0, %0, c1, c0, 1":"=r" (val));
+
+	if ((val & 0x2) == 0)
+		printk(KERN_WARNING "Warning: L2 cache not enabled. Check "
+		       "your bootloader. L2 off results in performance loss\n");
+	else
+		pr_info("OMAP3 L2 cache enabled\n");
+
+	return 0;
+}
+
+arch_initcall(omap3_check_l2cache);
+#endif /* CONFIG_ARCH_OMAP3 */