From: Paul Walmsley Date: Fri, 25 Jan 2008 08:20:08 +0000 (-0700) Subject: 3430ES2 clock: Add several 3430ES2-only clocks X-Git-Tag: v2.6.24-omap1~17 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=6213074ff576525772fdd906f99f522ca527c7a5;p=linux-2.6-omap-h63xx.git 3430ES2 clock: Add several 3430ES2-only clocks Add several OMAP3430ES2-only clocks: - DPLL5, which provides clock to onboard USB and USIM modules; - the Customer Programmable EFUSE; - MMC3; - SGX, the graphics module replacing GFX; - the bandgap temperature sensor; - USBHOST; - USB TLL (transceiverless link); - the Universal Subscriber Identity Module (USIM). The interface clock for USB TLL is on CM_ICLKEN3, which formerly was OMAP2430-only; so also convert OMAP2430_CM_ICLKEN3 to CM_ICLKEN3. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 49fff3c75f5..6ea0c1b43c0 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -9,8 +9,8 @@ * Written by Tuukka Tikkanen * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc * - * Copyright (C) 2007 Texas Instruments, Inc. - * Copyright (C) 2007 Nokia Corporation + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -2311,7 +2311,7 @@ static struct clk sdrc_ick = { .name = "sdrc_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3), + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP2430_EN_SDRC_SHIFT, .recalc = &followparent_recalc, }; diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index fd6388ab0d4..229d34fa40e 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -1,8 +1,8 @@ /* * OMAP3 clock framework * - * Copyright (C) 2007 Texas Instruments, Inc. - * Copyright (C) 2007 Nokia Corporation + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation * * Written by Paul Walmsley */ @@ -26,6 +26,7 @@ static void omap3_clkoutx2_recalc(struct clk *clk); * DPLL2 supplies clock to the IVA2. * DPLL3 supplies CORE domain clocks. * DPLL4 supplies peripheral clocks. + * DPLL5 supplies other peripheral clocks (USBHOST, USIM). */ /* PRM CLOCKS */ @@ -622,6 +623,52 @@ static struct clk emu_per_alwon_ck = { .recalc = &followparent_recalc, }; +/* DPLL5 */ +/* Supplies 120MHz clock, USIM source clock */ +/* Type: DPLL */ +/* 3430ES2 only */ +static const struct dpll_data dpll5_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), + .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, + .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), + .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, + .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, +}; + +static struct clk dpll5_ck = { + .name = "dpll5_ck", + .parent = &sys_ck, + .dpll_data = &dpll5_dd, + .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | + ALWAYS_ENABLED, + .recalc = &omap3_dpll_recalc, +}; + +static const struct clksel div16_dpll5m2_clksel[] = { + { .parent = &dpll5_ck, .rates = div16_dpll_rates }, + { .parent = NULL } +}; + +static struct clk dpll5_m2_ck = { + .name = "dpll5_m2_ck", + .parent = &dpll5_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), + .clksel_mask = OMAP3430ES2_DIV_120M_MASK, + .clksel = div16_dpll5m2_clksel, + .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk omap_120m_fck = { + .name = "omap_120m_fck", + .parent = &dpll5_m2_ck, + .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, + .recalc = &followparent_recalc, +}; /* CM EXTERNAL CLOCK OUTPUTS */ @@ -831,6 +878,47 @@ static struct clk gfx_cg2_ck = { .recalc = &followparent_recalc, }; +/* SGX power domain - 3430ES2 only */ + +static const struct clksel_rate sgx_core_rates[] = { + { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 4, .val = 1, .flags = RATE_IN_343X }, + { .div = 6, .val = 2, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel_rate sgx_96m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 }, +}; + +static const struct clksel sgx_clksel[] = { + { .parent = &core_ck, .rates = sgx_core_rates }, + { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, + { .parent = NULL }, +}; + +static struct clk sgx_fck = { + .name = "sgx_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, + .clksel = sgx_clksel, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk sgx_ick = { + .name = "sgx_ick", + .parent = &l3_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + /* CORE power domain */ static struct clk d2d_26m_fck = { @@ -874,6 +962,33 @@ static struct clk gpt11_fck = { .recalc = &omap2_clksel_recalc, }; +static struct clk cpefuse_fck = { + .name = "cpefuse_fck", + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk ts_fck = { + .name = "ts_fck", + .parent = &omap_32k_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_bit = OMAP3430ES2_EN_TS_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk usbtll_fck = { + .name = "usbtll_fck", + .parent = &omap_120m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + /* CORE 96M FCLK-derived clocks */ static struct clk core_96m_fck = { @@ -884,6 +999,16 @@ static struct clk core_96m_fck = { .recalc = &followparent_recalc, }; +static struct clk mmchs3_fck = { + .name = "mmchs_fck", + .id = 3, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + static struct clk mmchs2_fck = { .name = "mmchs_fck", .id = 2, @@ -1182,6 +1307,25 @@ static struct clk core_l4_ick = { .recalc = &followparent_recalc, }; +static struct clk usbtll_ick = { + .name = "usbtll_ick", + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk mmchs3_ick = { + .name = "mmchs_ick", + .id = 3, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + /* Intersystem Communication Registers - chassis mode only */ static struct clk icr_ick = { .name = "icr_ick", @@ -1568,8 +1712,91 @@ static struct clk cam_l4_ick = { .recalc = &followparent_recalc, }; +/* USBHOST - 3430ES2 only */ + +static struct clk usbhost_120m_fck = { + .name = "usbhost_120m_fck", + .parent = &omap_120m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk usbhost_48m_fck = { + .name = "usbhost_48m_fck", + .parent = &omap_48m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk usbhost_l3_ick = { + .name = "usbhost_l3_ick", + .parent = &l3_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk usbhost_l4_ick = { + .name = "usbhost_l4_ick", + .parent = &l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + +static struct clk usbhost_sar_fck = { + .name = "usbhost_sar_fck", + .parent = &osc_sys_ck, + .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), + .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + /* WKUP */ +static const struct clksel_rate usim_96m_rates[] = { + { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 8, .val = 5, .flags = RATE_IN_343X }, + { .div = 10, .val = 6, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel_rate usim_120m_rates[] = { + { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 8, .val = 8, .flags = RATE_IN_343X }, + { .div = 16, .val = 9, .flags = RATE_IN_343X }, + { .div = 20, .val = 10, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel usim_clksel[] = { + { .parent = &omap_96m_fck, .rates = usim_96m_rates }, + { .parent = &omap_120m_fck, .rates = usim_120m_rates }, + { .parent = &sys_ck, .rates = div2_rates }, + { .parent = NULL }, +}; + +/* 3430ES2 only */ +static struct clk usim_fck = { + .name = "usim_fck", + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, + .clksel = usim_clksel, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &omap2_clksel_recalc, +}; + static struct clk gpt1_fck = { .name = "gpt1_fck", .init = &omap2_init_clksel_parent, @@ -1614,6 +1841,17 @@ static struct clk wkup_l4_ick = { .recalc = &followparent_recalc, }; +/* 3430ES2 only */ +/* Never specifically named in the TRM, so we have to infer a likely name */ +static struct clk usim_ick = { + .name = "usim_ick", + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, + .flags = CLOCK_IN_OMAP3430ES2, + .recalc = &followparent_recalc, +}; + static struct clk wdt2_ick = { .name = "wdt2_ick", .parent = &wkup_l4_ick, @@ -2287,6 +2525,9 @@ static struct clk *onchip_34xx_clks[] __initdata = { &dpll4_m5x2_ck, &dpll4_m6x2_ck, &emu_per_alwon_ck, + &dpll5_ck, + &dpll5_m2_ck, + &omap_120m_fck, &clkout2_src_ck, &sys_clkout2, &corex2_fck, @@ -2299,10 +2540,16 @@ static struct clk *onchip_34xx_clks[] __initdata = { &gfx_l3_ick, &gfx_cg1_ck, &gfx_cg2_ck, + &sgx_fck, + &sgx_ick, &d2d_26m_fck, &gpt10_fck, &gpt11_fck, + &cpefuse_fck, + &ts_fck, + &usbtll_fck, &core_96m_fck, + &mmchs3_fck, &mmchs2_fck, &mspro_fck, &mmchs1_fck, @@ -2330,6 +2577,8 @@ static struct clk *onchip_34xx_clks[] __initdata = { &security_l3_ick, &pka_ick, &core_l4_ick, + &usbtll_ick, + &mmchs3_ick, &icr_ick, &aes2_ick, &sha12_ick, @@ -2370,11 +2619,18 @@ static struct clk *onchip_34xx_clks[] __initdata = { &cam_mclk, &cam_l3_ick, &cam_l4_ick, + &usbhost_120m_fck, + &usbhost_48m_fck, + &usbhost_l3_ick, + &usbhost_l4_ick, + &usbhost_sar_fck, + &usim_fck, &gpt1_fck, &wkup_32k_fck, &gpio1_fck, &wdt2_fck, &wkup_l4_ick, + &usim_ick, &wdt2_ick, &wdt1_ick, &gpio1_ick, diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index 2b10d3831d4..fc3dea630a5 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -4,8 +4,8 @@ /* * OMAP2/3 Clock Management (CM) register definitions * - * Copyright (C) 2007 Texas Instruments, Inc. - * Copyright (C) 2007 Nokia Corporation + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation * * Written by Paul Walmsley * @@ -61,6 +61,7 @@ static u32 __attribute__((unused)) cm_read_reg(void __iomem *addr) #define CM_ICLKEN1 0x0010 #define CM_ICLKEN CM_ICLKEN1 #define CM_ICLKEN2 0x0014 +#define CM_ICLKEN3 0x0018 #define CM_IDLEST1 0x0020 #define CM_IDLEST CM_IDLEST1 #define CM_IDLEST2 0x0024 @@ -80,7 +81,6 @@ static u32 __attribute__((unused)) cm_read_reg(void __iomem *addr) #define OMAP24XX_CM_AUTOIDLE3 0x0038 #define OMAP24XX_CM_AUTOIDLE4 0x003c -#define OMAP2430_CM_ICLKEN3 0x0018 #define OMAP2430_CM_IDLEST3 0x0028 @@ -110,6 +110,8 @@ static u32 __attribute__((unused)) cm_read_mod_reg(s16 module, s16 idx) #define OMAP_ST_GFX (1 << 0) #define OMAP3430_CM_CLKEN_PLL 0x0004 +#define OMAP3430ES2_CM_CLKEN2 0x0004 +#define OMAP3430ES2_CM_FCLKEN3 0x0008 #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 #define OMAP3430_CM_CLKSEL1 CM_CLKSEL @@ -118,6 +120,8 @@ static u32 __attribute__((unused)) cm_read_mod_reg(s16 module, s16 idx) #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 #define OMAP3430_CM_CLKSEL3 CM_CLKSTCTRL #define OMAP3430_CM_CLKSTST 0x004c +#define OMAP3430ES2_CM_CLKSEL4 0x004c +#define OMAP3430ES2_CM_CLKSEL5 0x0050 #define OMAP3430_CM_CLKSEL2_EMU 0x0050 #define OMAP3430_CM_CLKSEL3_EMU 0x0054 diff --git a/arch/arm/mach-omap2/cm_regbits_34xx.h b/arch/arm/mach-omap2/cm_regbits_34xx.h index e7cffa6d4d8..e31ff225039 100644 --- a/arch/arm/mach-omap2/cm_regbits_34xx.h +++ b/arch/arm/mach-omap2/cm_regbits_34xx.h @@ -4,8 +4,8 @@ /* * OMAP3430 Clock Management register bits * - * Copyright (C) 2007 Texas Instruments, Inc. - * Copyright (C) 2007 Nokia Corporation + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation * * Written by Paul Walmsley * @@ -19,6 +19,8 @@ /* Bits shared between registers */ /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ +#define OMAP3430ES2_EN_MMC3_MASK (1 << 30) +#define OMAP3430ES2_EN_MMC3_SHIFT 30 #define OMAP3430_EN_MSPRO (1 << 23) #define OMAP3430_EN_MSPRO_SHIFT 23 #define OMAP3430_EN_HDQ (1 << 22) @@ -30,6 +32,10 @@ #define OMAP3430_EN_SSI (1 << 0) #define OMAP3430_EN_SSI_SHIFT 0 +/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ +#define OMAP3430ES2_EN_USBTLL_SHIFT 2 +#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) + /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ #define OMAP3430_EN_WDT2 (1 << 5) #define OMAP3430_EN_WDT2_SHIFT 5 @@ -165,6 +171,12 @@ #define OMAP3430_EN_DES1 (1 << 0) #define OMAP3430_EN_DES1_SHIFT 0 +/* CM_FCLKEN3_CORE specific bits */ +#define OMAP3430ES2_EN_TS_SHIFT 1 +#define OMAP3430ES2_EN_TS_MASK (1 << 1) +#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 +#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) + /* CM_IDLEST1_CORE specific bits */ #define OMAP3430_ST_ICR (1 << 29) #define OMAP3430_ST_AES2 (1 << 28) @@ -296,19 +308,28 @@ /* CM_SLEEPDEP_GFX specific bits */ /* CM_CLKSTCTRL_GFX */ -#define OMAP3430_CLKTRCTRL_GFX_SHIFT 0 -#define OMAP3430_CLKTRCTRL_GFX_MASK (0x3 << 0) +#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 +#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) /* CM_CLKSTST_GFX */ -#define OMAP3430_CLKACTIVITY_GFX (1 << 0) +#define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0) + +/* CM_FCLKEN_SGX */ +#define OMAP3430ES2_EN_SGX_SHIFT 1 +#define OMAP3430ES2_EN_SGX_MASK (1 << 1) + +/* CM_CLKSEL_SGX */ +#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 +#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) /* CM_FCLKEN_WKUP specific bits */ +#define OMAP3430ES2_EN_USIMOCP_SHIFT 9 /* CM_ICLKEN_WKUP specific bits */ #define OMAP3430_EN_WDT1 (1 << 4) #define OMAP3430_EN_WDT1_SHIFT 4 #define OMAP3430_EN_32KSYNC (1 << 2) -#define OMAP3430_EN_32KSYNC_SHIFT 2 +#define OMAP3430_EN_32KSYNC_SHIFT 2 /* CM_IDLEST_WKUP specific bits */ #define OMAP3430_ST_WDT2 (1 << 5) @@ -330,10 +351,11 @@ #define OMAP3430_AUTO_GPT1_SHIFT 0 /* CM_CLKSEL_WKUP */ +#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) #define OMAP3430_CLKSEL_RM_SHIFT 1 #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) -#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) #define OMAP3430_CLKSEL_GPT1_SHIFT 0 +#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) /* CM_CLKEN_PLL */ #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 @@ -359,6 +381,13 @@ #define OMAP3430_EN_CORE_DPLL_SHIFT 0 #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) +/* CM_CLKEN2_PLL */ +#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 +#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) +#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) +#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 +#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) + /* CM_IDLEST_CKGEN */ #define OMAP3430_ST_54M_CLK (1 << 5) #define OMAP3430_ST_12M_CLK (1 << 4) @@ -394,6 +423,13 @@ #define OMAP3430_DIV_96M_SHIFT 0 #define OMAP3430_DIV_96M_MASK (0x1f << 0) +/* CM_CLKSEL4_PLL */ +#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) +#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) + +/* CM_CLKSEL5_PLL */ +#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) + /* CM_CLKOUT_CTRL */ #define OMAP3430_CLKOUT2_EN_SHIFT 7 #define OMAP3430_CLKOUT2_EN (1 << 7) @@ -583,4 +619,14 @@ #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) +/* CM_FCLKEN_USBHOST */ +#define OMAP3430ES2_EN_USBHOST2_SHIFT 1 +#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) +#define OMAP3430ES2_EN_USBHOST1_SHIFT 0 +#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) + +/* CM_ICLKEN_USBHOST */ +#define OMAP3430ES2_EN_USBHOST_SHIFT 0 +#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) + #endif diff --git a/arch/arm/mach-omap2/prcm_common.h b/arch/arm/mach-omap2/prcm_common.h index a2f8f50e9ef..cacb34086e3 100644 --- a/arch/arm/mach-omap2/prcm_common.h +++ b/arch/arm/mach-omap2/prcm_common.h @@ -4,8 +4,8 @@ /* * OMAP2/3 PRCM base and module definitions * - * Copyright (C) 2007 Texas Instruments, Inc. - * Copyright (C) 2007 Nokia Corporation + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation * * Written by Paul Walmsley * @@ -17,8 +17,12 @@ /* Module offsets from both CM_BASE & PRM_BASE */ -/* Offsets that are the same on 24xx and 34xx */ -/* Technically OCP_MOD is 34xx only, and PLL_MOD is CCR_MOD on 3430 */ +/* + * Offsets that are the same on 24xx and 34xx + * + * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is + * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2. + */ #define OCP_MOD 0x000 #define MPU_MOD 0x100 #define CORE_MOD 0x200 @@ -34,6 +38,7 @@ /* IVA2 module is < base on 3430 */ #define OMAP3430_IVA2_MOD -0x800 +#define OMAP3430ES2_SGX_MOD GFX_MOD #define OMAP3430_CCR_MOD PLL_MOD #define OMAP3430_DSS_MOD 0x600 #define OMAP3430_CAM_MOD 0x700 @@ -41,6 +46,7 @@ #define OMAP3430_EMU_MOD 0x900 #define OMAP3430_GR_MOD 0xa00 #define OMAP3430_NEON_MOD 0xb00 +#define OMAP3430ES2_USBHOST_MOD 0xc00 /* 24XX register bits shared between CM & PRM registers */ diff --git a/arch/arm/mach-omap2/prm_regbits_34xx.h b/arch/arm/mach-omap2/prm_regbits_34xx.h index 71ba8602bba..b4686bc345c 100644 --- a/arch/arm/mach-omap2/prm_regbits_34xx.h +++ b/arch/arm/mach-omap2/prm_regbits_34xx.h @@ -4,8 +4,8 @@ /* * OMAP3430 Power/Reset Management register bits * - * Copyright (C) 2007 Texas Instruments, Inc. - * Copyright (C) 2007 Nokia Corporation + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation * * Written by Paul Walmsley * @@ -211,6 +211,8 @@ /* PRM_SYSCONFIG specific bits */ /* PRM_IRQSTATUS_MPU specific bits */ +#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 +#define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25) #define OMAP3430_VC_TIMEOUTERR_ST (1 << 24) #define OMAP3430_VC_RAERR_ST (1 << 23) #define OMAP3430_VC_SAERR_ST (1 << 22) @@ -241,6 +243,8 @@ #define OMAP3430_FS_USB_WKUP_ST (1 << 1) /* PRM_IRQENABLE_MPU specific bits */ +#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 +#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25) #define OMAP3430_VC_TIMEOUTERR_EN (1 << 24) #define OMAP3430_VC_RAERR_EN (1 << 23) #define OMAP3430_VC_SAERR_EN (1 << 22) @@ -400,6 +404,9 @@ /* PM_PREPWSTST_CAM specific bits */ +/* PM_PWSTCTRL_USBHOST specific bits */ +#define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4) + /* RM_RSTST_PER specific bits */ /* PM_WKEN_PER specific bits */