From: Nick Piggin Date: Wed, 21 May 2008 14:10:56 +0000 (+1000) Subject: [POWERPC] Fix rmb to order cacheable vs. noncacheable X-Git-Tag: v2.6.26-rc7~27^2~10 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=598056d5af8fef1dbe8f96f5c2b641a528184e5a;p=linux-2.6-omap-h63xx.git [POWERPC] Fix rmb to order cacheable vs. noncacheable lwsync is explicitly defined not to have any effect on the ordering of accesses to device memory, so it cannot be used for rmb(). sync appears to be the only barrier which fits the bill. Signed-off-by: Nick Piggin Acked-by: Benjamin Herrenschmidt Signed-off-by: Paul Mackerras --- diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h index 2b6559a6d11..5235f875b93 100644 --- a/include/asm-powerpc/system.h +++ b/include/asm-powerpc/system.h @@ -34,7 +34,7 @@ * SMP since it is only used to order updates to system memory. */ #define mb() __asm__ __volatile__ ("sync" : : : "memory") -#define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory") +#define rmb() __asm__ __volatile__ ("sync" : : : "memory") #define wmb() __asm__ __volatile__ ("sync" : : : "memory") #define read_barrier_depends() do { } while(0)