From: Ralf Baechle Date: Tue, 14 Mar 2006 23:52:47 +0000 (+0000) Subject: [MIPS] Sibyte: Fix interrupt timer off by one bug. X-Git-Tag: v2.6.16~2^2~2 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=4308cb16286c96d980570cc5319173b524220c06;p=linux-2.6-omap-h63xx.git [MIPS] Sibyte: Fix interrupt timer off by one bug. From Dave Johnson : The timers need to be loaded with 1 less than the desired interval not the interval itself. Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index 511c89d65f3..adc0b5271a0 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c @@ -75,10 +75,10 @@ void sb1250_time_init(void) /* Disable the timer and set up the count */ __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); #ifdef CONFIG_SIMULATION - __raw_writeq(50000 / HZ, + __raw_writeq((50000 / HZ) - 1, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #else - __raw_writeq(1000000 / HZ, + __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #endif