From: Kumar Gala <galak@kernel.crashing.org>
Date: Thu, 4 Oct 2007 04:37:33 +0000 (-0500)
Subject: [POWERPC] FSL: Access PCIe LTSSM register with correct size
X-Git-Tag: v2.6.24-rc1~1450^2~57
X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=2fce1225af6f2d3bb9ffb4e6253400db61278594;p=linux-2.6-omap-h63xx.git

[POWERPC] FSL: Access PCIe LTSSM register with correct size

The LTSSM register is actual 32-bits wide so we should be doing a
dword access.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 98290f4ef3d..af090c93be1 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -160,8 +160,8 @@ static void __init quirk_fsl_pcie_transparent(struct pci_dev *dev)
 
 int __init fsl_pcie_check_link(struct pci_controller *hose)
 {
-	u16 val;
-	early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
+	u32 val;
+	early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
 	if (val < PCIE_LTSSM_L0)
 		return 1;
 	return 0;