From: Eric Anholt Date: Mon, 15 Sep 2008 20:13:34 +0000 (-0700) Subject: drm: G33-class hardware has a newer 965-style MCH (no DCC register). X-Git-Tag: v2.6.28-rc1~255^2~17 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=28af0a2767412937e8424364a8ece9b230bdbc83;p=linux-2.6-omap-h63xx.git drm: G33-class hardware has a newer 965-style MCH (no DCC register). Fixes bad software fallback rendering in Mesa in dual-channel configurations. d9a2470012588dc5313a5ac8bb2f03575af00e99 Signed-off-by: Dave Airlie --- diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 0c1b3a0834e..6b3f1e4a34a 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -96,7 +96,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) */ swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE; - } else if (!IS_I965G(dev) || IS_I965GM(dev)) { + } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) { uint32_t dcc; /* On 915-945 and GM965, channel interleave by the CPU is