From: Harvey Harrison Date: Wed, 5 Nov 2008 18:35:31 +0000 (-0800) Subject: xtensa: use the new byteorder headers X-Git-Tag: v2.6.29-rc1~194^2~4 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=206ead28377fee86b129637edada8c77816cc0d6;p=linux-2.6-omap-h63xx.git xtensa: use the new byteorder headers Signed-off-by: Harvey Harrison Signed-off-by: Chris Zankel --- diff --git a/include/asm-xtensa/byteorder.h b/include/asm-xtensa/byteorder.h index 765edf17a9a..07d10ad364d 100644 --- a/include/asm-xtensa/byteorder.h +++ b/include/asm-xtensa/byteorder.h @@ -14,7 +14,17 @@ #include #include -static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) +#ifdef __XTENSA_EL__ +# define __LITTLE_ENDIAN +#elif defined(__XTENSA_EB__) +# define __BIG_ENDIAN +#else +# error processor byte order undefined! +#endif + +#define __SWAB_64_THRU_32__ + +static inline __attribute_const__ __u32 __arch_swab32(__u32 x) { __u32 res; /* instruction sequence from Xtensa ISA release 2/2000 */ @@ -28,8 +38,9 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) ); return res; } +#define __arch_swab32 __arch_swab32 -static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) +static inline __attribute_const__ __u16 __arch_swab16(__u16 x) { /* Given that 'short' values are signed (i.e., can be negative), * we cannot assume that the upper 16-bits of the register are @@ -62,21 +73,8 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) return res; } +#define __arch_swab16 __arch_swab16 -#define __arch__swab32(x) ___arch__swab32(x) -#define __arch__swab16(x) ___arch__swab16(x) - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#ifdef __XTENSA_EL__ -# include -#elif defined(__XTENSA_EB__) -# include -#else -# error processor byte order undefined! -#endif +#include #endif /* _XTENSA_BYTEORDER_H */