From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 29 Jan 2008 10:14:54 +0000 (+0000)
Subject: [MIPS] tlbex: Cleanup handling of R2 hazards in TLB handlers.
X-Git-Tag: v2.6.25-rc1~1163^2~65
X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=161548bf3529d53398adb3451cdc781cc324fc1d;p=linux-2.6-omap-h63xx.git

[MIPS] tlbex: Cleanup handling of R2 hazards in TLB handlers.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index a61246d3533..511107f92d9 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -860,6 +860,12 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
 	case tlb_indexed: tlbw = i_tlbwi; break;
 	}
 
+	if (cpu_has_mips_r2) {
+		i_ehb(p);
+		tlbw(p);
+		return;
+	}
+
 	switch (current_cpu_type()) {
 	case CPU_R4000PC:
 	case CPU_R4000SC:
@@ -935,14 +941,6 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
 		tlbw(p);
 		break;
 
-	case CPU_4KEC:
-	case CPU_24K:
-	case CPU_34K:
-	case CPU_74K:
-		i_ehb(p);
-		tlbw(p);
-		break;
-
 	case CPU_RM9000:
 		/*
 		 * When the JTLB is updated by tlbwi or tlbwr, a subsequent