From: Matthew Fleming <matthew.fleming@imgtec.com>
Date: Thu, 2 Oct 2008 11:24:05 +0000 (+0100)
Subject: MMC: CSD and CID timeout values
X-Git-Tag: v2.6.28-rc1~701^2~2
X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=0d3e0460f307e84904968aad6cff97bd688583d8;p=linux-2.6-omap-h63xx.git

MMC: CSD and CID timeout values

The MMC spec states that the timeout for accessing the CSD and CID
registers is 64 clock cycles.

Signed-off-by: Matthew Fleming <matthew.fleming@imgtec.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
---

diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 64b05c6270f..9c50e6f1c23 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -248,8 +248,12 @@ mmc_send_cxd_data(struct mmc_card *card, struct mmc_host *host,
 
 	sg_init_one(&sg, data_buf, len);
 
-	if (card)
-		mmc_set_data_timeout(&data, card);
+	/*
+	 * The spec states that CSR and CID accesses have a timeout
+	 * of 64 clock cycles.
+	 */
+	data.timeout_ns = 0;
+	data.timeout_clks = 64;
 
 	mmc_wait_for_req(host, &mrq);