From: Imre Deak Date: Mon, 12 Jun 2006 15:17:33 +0000 (+0300) Subject: ARM: OMAP: SoSSI: fix write / read cycle to tw1 mapping X-Git-Tag: v2.6.17-omap1~37 X-Git-Url: http://pilppa.com/gitweb/?a=commitdiff_plain;h=0976dc5e2d1501c31a2a33009617516b04b6da6a;p=linux-2.6-omap-h63xx.git ARM: OMAP: SoSSI: fix write / read cycle to tw1 mapping A read / write cycle is defined by tw0 + tw1. It was wrongly assumed that the 1 cycle long CS active edge to read / write active edge is part of each cycle, thus we ended up with too low tw1 value -> too short cycle time. Signed-off-by: Imre Deak Signed-off-by: Juha Yrjola --- diff --git a/drivers/video/omap/sossi.c b/drivers/video/omap/sossi.c index 6e8142ba5f7..64dd0a46e51 100644 --- a/drivers/video/omap/sossi.c +++ b/drivers/video/omap/sossi.c @@ -239,7 +239,7 @@ static int calc_rd_timings(struct extif_timings *t) if (recyc <= reoff) recyc = reoff + 1; - tw1 = recyc - reoff; + tw1 = recyc - tw0; /* values less then 3 result in the SOSSI block resetting itself */ if (tw1 < 3) tw1 = 3; @@ -286,7 +286,7 @@ static int calc_wr_timings(struct extif_timings *t) if (wecyc <= weoff) wecyc = weoff + 1; - tw1 = wecyc - weoff; + tw1 = wecyc - tw0; /* values less then 3 result in the SOSSI block resetting itself */ if (tw1 < 3) tw1 = 3;