If the clock framework can't figure out how to enable a clock, return
-EINVAL to indicate that the clock cannot be enabled. Previously the
code returned 0, which indicated success.
Also fix the "clock.c: Enable for dpll_ck without enable code" boot
warning by marking dpll_ck as ALWAYS_ENABLED. This is not technically
true, since the DPLL can be bypassed; but since we currently have no
software infrastructure to control it directly, ALWAYS_ENABLED is a
sufficient fiction for dpll_ck.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
if (unlikely(clk->enable_reg == 0)) {
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
clk->name);
- return 0;
+ return -EINVAL;
}
if (clk->enable_reg == OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
return;
}
- if (clk->enable_reg == 0)
+ if (clk->enable_reg == 0) {
+ /*
+ * 'Independent' here refers to a clock which is not
+ * controlled by its parent.
+ */
+ printk(KERN_ERR "clock: clk_disable called on independent "
+ "clock %s which has no enable_reg\n", clk->name);
return;
+ }
if (clk->enable_reg == OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
omap2_clk_fixed_disable(clk);
.name = "dpll_ck",
.parent = &sys_ck, /* Can be func_32k also */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
+ RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1 |
+ ALWAYS_ENABLED,
.recalc = &omap2_clksel_recalc,
};