]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[IA64] move SAL_CACHE_FLUSH check later in boot
authorTroy Heber <troy.heber@hp.com>
Wed, 25 Oct 2006 20:46:15 +0000 (14:46 -0600)
committerTony Luck <tony.luck@intel.com>
Tue, 31 Oct 2006 22:32:10 +0000 (14:32 -0800)
The check to see if the firmware drops interrupts during a
SAL_CACHE_FLUSH is done to early in the boot. SAL_CACHE_FLUSH expects
to be able to make PAL calls in virtual mode, on some cell based
machines a fault occurs causing a MCA. This patch moves the check
after mmu_context_init so the TLB and VHPT are properly setup.

Signed-off-by Troy Heber <troy.heber@hp.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
arch/ia64/kernel/sal.c
arch/ia64/kernel/setup.c
include/asm-ia64/sal.h

index 642fdc7b969d5c4f6450f588e82e0f2a29064063..20bad78b5073d48ba454ee24131b01a81531861b 100644 (file)
@@ -223,12 +223,13 @@ static void __init sal_desc_ap_wakeup(void *p) { }
  */
 static int sal_cache_flush_drops_interrupts;
 
-static void __init
+void __init
 check_sal_cache_flush (void)
 {
        unsigned long flags;
        int cpu;
-       u64 vector;
+       u64 vector, cache_type = 3;
+       struct ia64_sal_retval isrv;
 
        cpu = get_cpu();
        local_irq_save(flags);
@@ -243,7 +244,10 @@ check_sal_cache_flush (void)
        while (!ia64_get_irr(IA64_TIMER_VECTOR))
                cpu_relax();
 
-       ia64_sal_cache_flush(3);
+       SAL_CALL(isrv, SAL_CACHE_FLUSH, cache_type, 0, 0, 0, 0, 0, 0);
+
+       if (isrv.status)
+               printk(KERN_ERR "SAL_CAL_FLUSH failed with %ld\n", isrv.status);
 
        if (ia64_get_irr(IA64_TIMER_VECTOR)) {
                vector = ia64_get_ivr();
@@ -331,7 +335,6 @@ ia64_sal_init (struct ia64_sal_systab *systab)
                p += SAL_DESC_SIZE(*p);
        }
 
-       check_sal_cache_flush();
 }
 
 int
index c4caa800349220d22b69dc25ac12e490d059c85d..d10404a4175630c6d18ccfe5aa5e265face6ec68 100644 (file)
@@ -457,6 +457,8 @@ setup_arch (char **cmdline_p)
        cpu_init();     /* initialize the bootstrap CPU */
        mmu_context_init();     /* initialize context_id bitmap */
 
+       check_sal_cache_flush();
+
 #ifdef CONFIG_ACPI
        acpi_boot_init();
 #endif
index 0b210abbe0033ce06a1f7c1db28e8bcf0395ef6e..d000689d91421f6b0103660fe047146b166d50d0 100644 (file)
@@ -659,6 +659,7 @@ ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
 }
 
 extern s64 ia64_sal_cache_flush (u64 cache_type);
+extern void __init check_sal_cache_flush (void);
 
 /* Initialize all the processor and platform level instruction and data caches */
 static inline s64