ARM: OMAP: Clock updates for OMAP3430

Signed-off-by: Syed Mohammed Khasim  <x0khasim@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 62faecdbf094b7722e9acdfa2ef70b5a2a48de26..8afdde5675f7ba8f2c7d94830480f325faaf6f61 100644 (file)
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -58,11 +58,15 @@ static u8 cpu_mask;
 /* Recalculate SYST_CLK */
 static void omap2_sys_clk_recalc(struct clk * clk)
 {
-       u32 div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
-       /* Test if ext clk divided by 1 or 2 */
-       div &= (0x3 << OMAP_SYSCLKDIV_SHIFT);
-       div >>= clk->rate_offset;
-       clk->rate = (clk->parent->rate / div);
+       u32 div;
+
+       if (!cpu_is_omap34xx()) {
+               div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
+               /* Test if ext clk divided by 1 or 2 */
+               div &= (0x3 << OMAP_SYSCLKDIV_SHIFT);
+               div >>= clk->rate_offset;
+               clk->rate = (clk->parent->rate / div);
+       }
        propagate_rate(clk);
 }
 
@@ -1181,7 +1185,7 @@ int __init omap2_clk_init(void)
                        continue;
                }
 
-               if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
+               if ((*clkp)->flags & CLOCK_IN_OMAP243X && (cpu_is_omap2430() || cpu_is_omap34xx())) {
                        clk_register(*clkp);
                        continue;
                }

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 8f19641bfe2e0a5ffa01752cdd54ba795c3b03f4..940545f659e9993dbe051fb146e9f7f5817ff238 100644 (file)
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -39,6 +39,7 @@ static u32 omap2_clksel_get_divisor(struct clk *clk);
 
 #define RATE_IN_242X   (1 << 0)
 #define RATE_IN_243X   (1 << 1)
+#define RATE_IN_343X   (1 << 2)
 
 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP