return 1;
}
-struct omap_mbox_ops omap1_mbox_ops = {
+static struct omap_mbox_ops omap1_mbox_ops = {
.type = OMAP_MBOX_TYPE1,
.fifo_read = omap1_mbox_fifo_read,
.fifo_write = omap1_mbox_fifo_write,
#define MAILBOX_IRQSTATUS_3 0x118
#define MAILBOX_IRQENABLE_3 0x11c
-unsigned long mbox_base;
+static unsigned long mbox_base;
#define MAILBOX_IRQ_NOTFULL(n) (1 << (2 * (n) + 1))
#define MAILBOX_IRQ_NEWMSG(n) (1 << (2 * (n)))
u32 notfull_bit;
};
-struct clk *mbox_ick_handle;
+static struct clk *mbox_ick_handle;
static inline unsigned int mbox_read_reg(unsigned int reg)
{
return (enable & status & bit);
}
-struct omap_mbox_ops omap2_mbox_ops = {
+static struct omap_mbox_ops omap2_mbox_ops = {
.type = OMAP_MBOX_TYPE2,
.startup = omap2_mbox_startup,
.shutdown = omap2_mbox_shutdown,
},
};
-int __init omap2_mbox_init(void)
+static int __init omap2_mbox_init(void)
{
return platform_driver_register(&omap2_mbox_driver);
}
#ifndef __ARCH_ARM_PLAT_MAILBOX_H
#define __ARCH_ARM_PLAT_MAILBOX_H
-#define MBOX_NAME_LEN 255
-
/*
* Mailbox sequence bit API
*/