[ARM] 4080/1: Fix for the SSCR0_SlotsPerFrm macro

The SSCR0_SlotsPerFrm macro writes a 3-bit value to bits [2:0], while the correct location of FRDC in SSCR0 is at bits [26:24]. This patch adds the missing "<< 24".

Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 083e03c5639ff4a9c1dfd68364bb5144a7a4df11..f8f34505f4709aba8ffeb8b2d6dd3cb1efb6aa9d 100644 (file)
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1626,7 +1626,7 @@
 #define SSCR0_RIM      (1 << 22)       /* Receive FIFO overrrun interrupt mask */
 #define SSCR0_TUM      (1 << 23)       /* Transmit FIFO underrun interrupt mask */
 #define SSCR0_FRDC     (0x07000000)    /* Frame rate divider control (mask) */
-#define SSCR0_SlotsPerFrm(x) ((x) - 1) /* Time slots per frame [1..8] */
+#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
 #define SSCR0_ADC      (1 << 30)       /* Audio clock select */
 #define SSCR0_MOD      (1 << 31)       /* Mode (normal or network) */
 #endif