/*
* Functions below are used on OpenFirmware machines.
*/
-static void __openfirmware
+static void
make_one_node_map(struct device_node* node, u8 pci_bus)
{
int *bus_range;
}
}
-void __openfirmware
+void
pcibios_make_OF_bus_map(void)
{
int i;
typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
-static struct device_node* __openfirmware
+static struct device_node*
scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
{
struct device_node* sub_node;
return 0;
}
-static struct device_node* __openfirmware
+static struct device_node*
scan_OF_childs_for_device(struct device_node* node, u8 bus, u8 dev_fn)
{
u8 filter_data[2] = {bus, dev_fn};
return NULL;
}
-static int __openfirmware
+static int
find_OF_pci_device_filter(struct device_node* node, void* data)
{
return ((void *)node == data);
* Assume here that all clock rates are the same in a
* smp system. -- Cort
*/
-int __openfirmware
+int
of_show_percpuinfo(struct seq_file *m, int i)
{
struct device_node *cpu_node;
* limit the bus number to 3 bits
*/
-int __chrp gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
+int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
int len, u32 *val)
{
volatile void __iomem *cfg_data;
return PCIBIOS_SUCCESSFUL;
}
-int __chrp gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
+int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
int len, u32 val)
{
volatile void __iomem *cfg_data;
/*
* Access functions for PCI config space using RTAS calls.
*/
-int __chrp
+int
rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
{
return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
}
-int __chrp
+int
rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 val)
{
"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
};
-int __chrp
+int
chrp_show_cpuinfo(struct seq_file *m)
{
int i, sdramen;
pci_create_OF_bus_map();
}
-void __chrp
+void
chrp_event_scan(void)
{
unsigned char log[1024];
ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
}
-void __chrp
+void
chrp_restart(char *cmd)
{
printk("RTAS system-reboot returned %d\n",
for (;;);
}
-void __chrp
+void
chrp_power_off(void)
{
/* allow power on only with power button press */
for (;;);
}
-void __chrp
+void
chrp_halt(void)
{
chrp_power_off();
}
-u_int __chrp
+u_int
chrp_irq_canonicalize(u_int irq)
{
if (irq == 2)
if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
}
-void __chrp
+void
rtas_display_progress(char *s, unsigned short hex)
{
int width;
call_rtas( "display-character", 1, 1, NULL, ' ' );
}
-void __chrp
+void
rtas_indicator_progress(char *s, unsigned short hex)
{
call_rtas("set-indicator", 3, 1, NULL, 6, 0, hex);
}
/* CHRP with openpic */
-struct smp_ops_t chrp_smp_ops __chrpdata = {
+struct smp_ops_t chrp_smp_ops = {
.message_pass = smp_openpic_message_pass,
.probe = smp_chrp_probe,
.kick_cpu = smp_chrp_kick_cpu,
return 0;
}
-int __chrp chrp_cmos_clock_read(int addr)
+int chrp_cmos_clock_read(int addr)
{
if (nvram_as1 != 0)
outb(addr>>8, nvram_as1);
return (inb(nvram_data));
}
-void __chrp chrp_cmos_clock_write(unsigned long val, int addr)
+void chrp_cmos_clock_write(unsigned long val, int addr)
{
if (nvram_as1 != 0)
outb(addr>>8, nvram_as1);
/*
* Set the hardware clock. -- Cort
*/
-int __chrp chrp_set_rtc_time(unsigned long nowtime)
+int chrp_set_rtc_time(unsigned long nowtime)
{
unsigned char save_control, save_freq_select;
struct rtc_time tm;
return 0;
}
-unsigned long __chrp chrp_get_rtc_time(void)
+unsigned long chrp_get_rtc_time(void)
{
unsigned int year, mon, day, hour, min, sec;
int uip, i;
static void backlight_callback(void *);
static DECLARE_WORK(backlight_work, backlight_callback, NULL);
-void __pmac register_backlight_controller(struct backlight_controller *ctrler,
+void register_backlight_controller(struct backlight_controller *ctrler,
void *data, char *type)
{
struct device_node* bk_node;
}
EXPORT_SYMBOL(register_backlight_controller);
-void __pmac unregister_backlight_controller(struct backlight_controller
+void unregister_backlight_controller(struct backlight_controller
*ctrler, void *data)
{
/* We keep the current backlight level (for now) */
}
EXPORT_SYMBOL(unregister_backlight_controller);
-static int __pmac __set_backlight_enable(int enable)
+static int __set_backlight_enable(int enable)
{
int rc;
release_console_sem();
return rc;
}
-int __pmac set_backlight_enable(int enable)
+int set_backlight_enable(int enable)
{
if (!backlighter)
return -ENODEV;
EXPORT_SYMBOL(set_backlight_enable);
-int __pmac get_backlight_enable(void)
+int get_backlight_enable(void)
{
if (!backlighter)
return -ENODEV;
}
EXPORT_SYMBOL(get_backlight_enable);
-static int __pmac __set_backlight_level(int level)
+static int __set_backlight_level(int level)
{
int rc = 0;
}
return rc;
}
-int __pmac set_backlight_level(int level)
+int set_backlight_level(int level)
{
if (!backlighter)
return -ENODEV;
EXPORT_SYMBOL(set_backlight_level);
-int __pmac get_backlight_level(void)
+int get_backlight_level(void)
{
if (!backlighter)
return -ENODEV;
/* Switch CPU speed under 750FX CPU control
*/
-static int __pmac cpu_750fx_cpu_speed(int low_speed)
+static int cpu_750fx_cpu_speed(int low_speed)
{
u32 hid2;
return 0;
}
-static unsigned int __pmac cpu_750fx_get_cpu_speed(void)
+static unsigned int cpu_750fx_get_cpu_speed(void)
{
if (mfspr(SPRN_HID1) & HID1_PS)
return low_freq;
}
/* Switch CPU speed using DFS */
-static int __pmac dfs_set_cpu_speed(int low_speed)
+static int dfs_set_cpu_speed(int low_speed)
{
if (low_speed == 0) {
/* ramping up, set voltage first */
return 0;
}
-static unsigned int __pmac dfs_get_cpu_speed(void)
+static unsigned int dfs_get_cpu_speed(void)
{
if (mfspr(SPRN_HID1) & HID1_DFS)
return low_freq;
/* Switch CPU speed using slewing GPIOs
*/
-static int __pmac gpios_set_cpu_speed(int low_speed)
+static int gpios_set_cpu_speed(int low_speed)
{
int gpio, timeout = 0;
/* Switch CPU speed under PMU control
*/
-static int __pmac pmu_set_cpu_speed(int low_speed)
+static int pmu_set_cpu_speed(int low_speed)
{
struct adb_request req;
unsigned long save_l2cr;
return 0;
}
-static int __pmac do_set_cpu_speed(int speed_mode, int notify)
+static int do_set_cpu_speed(int speed_mode, int notify)
{
struct cpufreq_freqs freqs;
unsigned long l3cr;
return 0;
}
-static unsigned int __pmac pmac_cpufreq_get_speed(unsigned int cpu)
+static unsigned int pmac_cpufreq_get_speed(unsigned int cpu)
{
return cur_freq;
}
-static int __pmac pmac_cpufreq_verify(struct cpufreq_policy *policy)
+static int pmac_cpufreq_verify(struct cpufreq_policy *policy)
{
return cpufreq_frequency_table_verify(policy, pmac_cpu_freqs);
}
-static int __pmac pmac_cpufreq_target( struct cpufreq_policy *policy,
+static int pmac_cpufreq_target( struct cpufreq_policy *policy,
unsigned int target_freq,
unsigned int relation)
{
return do_set_cpu_speed(newstate, 1);
}
-unsigned int __pmac pmac_get_one_cpufreq(int i)
+unsigned int pmac_get_one_cpufreq(int i)
{
/* Supports only one CPU for now */
return (i == 0) ? cur_freq : 0;
}
-static int __pmac pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
+static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
if (policy->cpu != 0)
return -ENODEV;
return cpufreq_frequency_table_cpuinfo(policy, pmac_cpu_freqs);
}
-static u32 __pmac read_gpio(struct device_node *np)
+static u32 read_gpio(struct device_node *np)
{
u32 *reg = (u32 *)get_property(np, "reg", NULL);
u32 offset;
return offset;
}
-static int __pmac pmac_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
+static int pmac_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
{
/* Ok, this could be made a bit smarter, but let's be robust for now. We
* always force a speed change to high speed before sleep, to make sure
return 0;
}
-static int __pmac pmac_cpufreq_resume(struct cpufreq_policy *policy)
+static int pmac_cpufreq_resume(struct cpufreq_policy *policy)
{
/* If we resume, first check if we have a get() function */
if (get_speed_proc)
};
-static int __pmac pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
+static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
{
struct device_node *volt_gpio_np = of_find_node_by_name(NULL,
"voltage-gpio");
return 0;
}
-static int __pmac pmac_cpufreq_init_7447A(struct device_node *cpunode)
+static int pmac_cpufreq_init_7447A(struct device_node *cpunode)
{
struct device_node *volt_gpio_np;
return 0;
}
-static int __pmac pmac_cpufreq_init_750FX(struct device_node *cpunode)
+static int pmac_cpufreq_init_750FX(struct device_node *cpunode)
{
struct device_node *volt_gpio_np;
u32 pvr, *value;
* We use a single global lock to protect accesses. Each driver has
* to take care of its own locking
*/
-static DEFINE_SPINLOCK(feature_lock __pmacdata);
+static DEFINE_SPINLOCK(feature_lock);
#define LOCK(flags) spin_lock_irqsave(&feature_lock, flags);
#define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags);
/*
* Instance of some macio stuffs
*/
-struct macio_chip macio_chips[MAX_MACIO_CHIPS] __pmacdata;
+struct macio_chip macio_chips[MAX_MACIO_CHIPS];
-struct macio_chip* __pmac macio_find(struct device_node* child, int type)
+struct macio_chip* macio_find(struct device_node* child, int type)
{
while(child) {
int i;
}
EXPORT_SYMBOL_GPL(macio_find);
-static const char* macio_names[] __pmacdata =
+static const char* macio_names[] =
{
"Unknown",
"Grand Central",
#define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v)))
#define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
-static struct device_node* uninorth_node __pmacdata;
-static u32 __iomem * uninorth_base __pmacdata;
-static u32 uninorth_rev __pmacdata;
-static int uninorth_u3 __pmacdata;
+static struct device_node* uninorth_node;
+static u32 __iomem * uninorth_base;
+static u32 uninorth_rev;
+static int uninorth_u3;
static void __iomem *u3_ht;
/*
struct feature_table_entry* features;
unsigned long board_flags;
};
-static struct pmac_mb_def pmac_mb __pmacdata;
+static struct pmac_mb_def pmac_mb;
/*
* Here are the chip specific feature functions
*/
-static inline int __pmac
+static inline int
simple_feature_tweak(struct device_node* node, int type, int reg, u32 mask, int value)
{
struct macio_chip* macio;
#ifndef CONFIG_POWER4
-static long __pmac
+static long
ohare_htw_scc_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio;
return 0;
}
-static long __pmac
+static long
ohare_floppy_enable(struct device_node* node, long param, long value)
{
return simple_feature_tweak(node, macio_ohare,
OHARE_FCR, OH_FLOPPY_ENABLE, value);
}
-static long __pmac
+static long
ohare_mesh_enable(struct device_node* node, long param, long value)
{
return simple_feature_tweak(node, macio_ohare,
OHARE_FCR, OH_MESH_ENABLE, value);
}
-static long __pmac
+static long
ohare_ide_enable(struct device_node* node, long param, long value)
{
switch(param) {
}
}
-static long __pmac
+static long
ohare_ide_reset(struct device_node* node, long param, long value)
{
switch(param) {
}
}
-static long __pmac
+static long
ohare_sleep_state(struct device_node* node, long param, long value)
{
struct macio_chip* macio = &macio_chips[0];
return 0;
}
-static long __pmac
+static long
heathrow_modem_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio;
return 0;
}
-static long __pmac
+static long
heathrow_floppy_enable(struct device_node* node, long param, long value)
{
return simple_feature_tweak(node, macio_unknown,
value);
}
-static long __pmac
+static long
heathrow_mesh_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio;
return 0;
}
-static long __pmac
+static long
heathrow_ide_enable(struct device_node* node, long param, long value)
{
switch(param) {
}
}
-static long __pmac
+static long
heathrow_ide_reset(struct device_node* node, long param, long value)
{
switch(param) {
}
}
-static long __pmac
+static long
heathrow_bmac_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio;
return 0;
}
-static long __pmac
+static long
heathrow_sound_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio;
return 0;
}
-static u32 save_fcr[6] __pmacdata;
-static u32 save_mbcr __pmacdata;
-static u32 save_gpio_levels[2] __pmacdata;
-static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT] __pmacdata;
-static u8 save_gpio_normal[KEYLARGO_GPIO_CNT] __pmacdata;
-static u32 save_unin_clock_ctl __pmacdata;
-static struct dbdma_regs save_dbdma[13] __pmacdata;
-static struct dbdma_regs save_alt_dbdma[13] __pmacdata;
+static u32 save_fcr[6];
+static u32 save_mbcr;
+static u32 save_gpio_levels[2];
+static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT];
+static u8 save_gpio_normal[KEYLARGO_GPIO_CNT];
+static u32 save_unin_clock_ctl;
+static struct dbdma_regs save_dbdma[13];
+static struct dbdma_regs save_alt_dbdma[13];
-static void __pmac
+static void
dbdma_save(struct macio_chip* macio, struct dbdma_regs* save)
{
int i;
}
}
-static void __pmac
+static void
dbdma_restore(struct macio_chip* macio, struct dbdma_regs* save)
{
int i;
}
}
-static void __pmac
+static void
heathrow_sleep(struct macio_chip* macio, int secondary)
{
if (secondary) {
(void)MACIO_IN32(HEATHROW_FCR);
}
-static void __pmac
+static void
heathrow_wakeup(struct macio_chip* macio, int secondary)
{
if (secondary) {
}
}
-static long __pmac
+static long
heathrow_sleep_state(struct device_node* node, long param, long value)
{
if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
return 0;
}
-static long __pmac
+static long
core99_scc_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio;
return 0;
}
-static long __pmac
+static long
core99_modem_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio;
return 0;
}
-static long __pmac
+static long
pangea_modem_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio;
return 0;
}
-static long __pmac
+static long
core99_ata100_enable(struct device_node* node, long value)
{
unsigned long flags;
return 0;
}
-static long __pmac
+static long
core99_ide_enable(struct device_node* node, long param, long value)
{
/* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2
}
}
-static long __pmac
+static long
core99_ide_reset(struct device_node* node, long param, long value)
{
switch(param) {
}
}
-static long __pmac
+static long
core99_gmac_enable(struct device_node* node, long param, long value)
{
unsigned long flags;
return 0;
}
-static long __pmac
+static long
core99_gmac_phy_reset(struct device_node* node, long param, long value)
{
unsigned long flags;
return 0;
}
-static long __pmac
+static long
core99_sound_chip_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio;
return 0;
}
-static long __pmac
+static long
core99_airport_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio;
}
#ifdef CONFIG_SMP
-static long __pmac
+static long
core99_reset_cpu(struct device_node* node, long param, long value)
{
unsigned int reset_io = 0;
}
#endif /* CONFIG_SMP */
-static long __pmac
+static long
core99_usb_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio;
return 0;
}
-static long __pmac
+static long
core99_firewire_enable(struct device_node* node, long param, long value)
{
unsigned long flags;
return 0;
}
-static long __pmac
+static long
core99_firewire_cable_power(struct device_node* node, long param, long value)
{
unsigned long flags;
return 0;
}
-static long __pmac
+static long
intrepid_aack_delay_enable(struct device_node* node, long param, long value)
{
unsigned long flags;
#endif /* CONFIG_POWER4 */
-static long __pmac
+static long
core99_read_gpio(struct device_node* node, long param, long value)
{
struct macio_chip* macio = &macio_chips[0];
}
-static long __pmac
+static long
core99_write_gpio(struct device_node* node, long param, long value)
{
struct macio_chip* macio = &macio_chips[0];
#ifdef CONFIG_POWER4
-static long __pmac
+static long
g5_gmac_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio = &macio_chips[0];
return 0;
}
-static long __pmac
+static long
g5_fw_enable(struct device_node* node, long param, long value)
{
struct macio_chip* macio = &macio_chips[0];
return 0;
}
-static long __pmac
+static long
g5_mpic_enable(struct device_node* node, long param, long value)
{
unsigned long flags;
}
#ifdef CONFIG_SMP
-static long __pmac
+static long
g5_reset_cpu(struct device_node* node, long param, long value)
{
unsigned int reset_io = 0;
* This takes the second CPU off the bus on dual CPU machines
* running UP
*/
-void __pmac g5_phy_disable_cpu1(void)
+void g5_phy_disable_cpu1(void)
{
UN_OUT(U3_API_PHY_CONFIG_1, 0);
}
#ifndef CONFIG_POWER4
-static void __pmac
+static void
keylargo_shutdown(struct macio_chip* macio, int sleep_mode)
{
u32 temp;
(void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
}
-static void __pmac
+static void
pangea_shutdown(struct macio_chip* macio, int sleep_mode)
{
u32 temp;
(void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
}
-static void __pmac
+static void
intrepid_shutdown(struct macio_chip* macio, int sleep_mode)
{
u32 temp;
}
-void __pmac pmac_tweak_clock_spreading(int enable)
+void pmac_tweak_clock_spreading(int enable)
{
struct macio_chip* macio = &macio_chips[0];
}
-static int __pmac
+static int
core99_sleep(void)
{
struct macio_chip* macio;
return 0;
}
-static int __pmac
+static int
core99_wake_up(void)
{
struct macio_chip* macio;
return 0;
}
-static long __pmac
+static long
core99_sleep_state(struct device_node* node, long param, long value)
{
/* Param == 1 means to enter the "fake sleep" mode that is
#endif /* CONFIG_POWER4 */
-static long __pmac
+static long
generic_dev_can_wake(struct device_node* node, long param, long value)
{
/* Todo: eventually check we are really dealing with on-board
return 0;
}
-static long __pmac
+static long
generic_get_mb_info(struct device_node* node, long param, long value)
{
switch(param) {
/* Used on any machine
*/
-static struct feature_table_entry any_features[] __pmacdata = {
+static struct feature_table_entry any_features[] = {
{ PMAC_FTR_GET_MB_INFO, generic_get_mb_info },
{ PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake },
{ 0, NULL }
* 2400,3400 and 3500 series powerbooks. Some older desktops seem
* to have issues with turning on/off those asic cells
*/
-static struct feature_table_entry ohare_features[] __pmacdata = {
+static struct feature_table_entry ohare_features[] = {
{ PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
{ PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable },
{ PMAC_FTR_MESH_ENABLE, ohare_mesh_enable },
* Separated as some features couldn't be properly tested
* and the serial port control bits appear to confuse it.
*/
-static struct feature_table_entry heathrow_desktop_features[] __pmacdata = {
+static struct feature_table_entry heathrow_desktop_features[] = {
{ PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
{ PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
{ PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
/* Heathrow based laptop, that is the Wallstreet and mainstreet
* powerbooks.
*/
-static struct feature_table_entry heathrow_laptop_features[] __pmacdata = {
+static struct feature_table_entry heathrow_laptop_features[] = {
{ PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
{ PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
{ PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
/* Paddington based machines
* The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4.
*/
-static struct feature_table_entry paddington_features[] __pmacdata = {
+static struct feature_table_entry paddington_features[] = {
{ PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
{ PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
{ PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
* chipset. The pangea chipset is the "combo" UniNorth/KeyLargo
* used on iBook2 & iMac "flow power".
*/
-static struct feature_table_entry core99_features[] __pmacdata = {
+static struct feature_table_entry core99_features[] = {
{ PMAC_FTR_SCC_ENABLE, core99_scc_enable },
{ PMAC_FTR_MODEM_ENABLE, core99_modem_enable },
{ PMAC_FTR_IDE_ENABLE, core99_ide_enable },
/* RackMac
*/
-static struct feature_table_entry rackmac_features[] __pmacdata = {
+static struct feature_table_entry rackmac_features[] = {
{ PMAC_FTR_SCC_ENABLE, core99_scc_enable },
{ PMAC_FTR_IDE_ENABLE, core99_ide_enable },
{ PMAC_FTR_IDE_RESET, core99_ide_reset },
/* Pangea features
*/
-static struct feature_table_entry pangea_features[] __pmacdata = {
+static struct feature_table_entry pangea_features[] = {
{ PMAC_FTR_SCC_ENABLE, core99_scc_enable },
{ PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
{ PMAC_FTR_IDE_ENABLE, core99_ide_enable },
/* Intrepid features
*/
-static struct feature_table_entry intrepid_features[] __pmacdata = {
+static struct feature_table_entry intrepid_features[] = {
{ PMAC_FTR_SCC_ENABLE, core99_scc_enable },
{ PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
{ PMAC_FTR_IDE_ENABLE, core99_ide_enable },
/* G5 features
*/
-static struct feature_table_entry g5_features[] __pmacdata = {
+static struct feature_table_entry g5_features[] = {
{ PMAC_FTR_GMAC_ENABLE, g5_gmac_enable },
{ PMAC_FTR_1394_ENABLE, g5_fw_enable },
{ PMAC_FTR_ENABLE_MPIC, g5_mpic_enable },
#endif /* CONFIG_POWER4 */
-static struct pmac_mb_def pmac_mb_defs[] __pmacdata = {
+static struct pmac_mb_def pmac_mb_defs[] = {
#ifndef CONFIG_POWER4
/*
* Desktops
/*
* The toplevel feature_call callback
*/
-long __pmac
+long
pmac_do_feature_call(unsigned int selector, ...)
{
struct device_node* node;
* Early video resume hook
*/
-static void (*pmac_early_vresume_proc)(void *data) __pmacdata;
-static void *pmac_early_vresume_data __pmacdata;
+static void (*pmac_early_vresume_proc)(void *data);
+static void *pmac_early_vresume_data;
void pmac_set_early_video_resume(void (*proc)(void *data), void *data)
{
}
EXPORT_SYMBOL(pmac_set_early_video_resume);
-void __pmac pmac_call_early_video_resume(void)
+void pmac_call_early_video_resume(void)
{
if (pmac_early_vresume_proc)
pmac_early_vresume_proc(pmac_early_vresume_data);
* AGP related suspend/resume code
*/
-static struct pci_dev *pmac_agp_bridge __pmacdata;
-static int (*pmac_agp_suspend)(struct pci_dev *bridge) __pmacdata;
-static int (*pmac_agp_resume)(struct pci_dev *bridge) __pmacdata;
+static struct pci_dev *pmac_agp_bridge;
+static int (*pmac_agp_suspend)(struct pci_dev *bridge);
+static int (*pmac_agp_resume)(struct pci_dev *bridge);
-void __pmac pmac_register_agp_pm(struct pci_dev *bridge,
+void pmac_register_agp_pm(struct pci_dev *bridge,
int (*suspend)(struct pci_dev *bridge),
int (*resume)(struct pci_dev *bridge))
{
}
EXPORT_SYMBOL(pmac_register_agp_pm);
-void __pmac pmac_suspend_agp_for_card(struct pci_dev *dev)
+void pmac_suspend_agp_for_card(struct pci_dev *dev)
{
if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL)
return;
}
EXPORT_SYMBOL(pmac_suspend_agp_for_card);
-void __pmac pmac_resume_agp_for_card(struct pci_dev *dev)
+void pmac_resume_agp_for_card(struct pci_dev *dev)
{
if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL)
return;
static int (*core99_write_bank)(int bank, u8* datas);
static int (*core99_erase_bank)(int bank);
-static char *nvram_image __pmacdata;
+static char *nvram_image;
-static unsigned char __pmac core99_nvram_read_byte(int addr)
+static unsigned char core99_nvram_read_byte(int addr)
{
if (nvram_image == NULL)
return 0xff;
return nvram_image[addr];
}
-static void __pmac core99_nvram_write_byte(int addr, unsigned char val)
+static void core99_nvram_write_byte(int addr, unsigned char val)
{
if (nvram_image == NULL)
return;
}
-static unsigned char __openfirmware direct_nvram_read_byte(int addr)
+static unsigned char direct_nvram_read_byte(int addr)
{
return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
}
-static void __openfirmware direct_nvram_write_byte(int addr, unsigned char val)
+static void direct_nvram_write_byte(int addr, unsigned char val)
{
out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
}
-static unsigned char __pmac indirect_nvram_read_byte(int addr)
+static unsigned char indirect_nvram_read_byte(int addr)
{
unsigned char val;
unsigned long flags;
return val;
}
-static void __pmac indirect_nvram_write_byte(int addr, unsigned char val)
+static void indirect_nvram_write_byte(int addr, unsigned char val)
{
unsigned long flags;
#ifdef CONFIG_ADB_PMU
-static void __pmac pmu_nvram_complete(struct adb_request *req)
+static void pmu_nvram_complete(struct adb_request *req)
{
if (req->arg)
complete((struct completion *)req->arg);
}
-static unsigned char __pmac pmu_nvram_read_byte(int addr)
+static unsigned char pmu_nvram_read_byte(int addr)
{
struct adb_request req;
DECLARE_COMPLETION(req_complete);
return req.reply[0];
}
-static void __pmac pmu_nvram_write_byte(int addr, unsigned char val)
+static void pmu_nvram_write_byte(int addr, unsigned char val)
{
struct adb_request req;
DECLARE_COMPLETION(req_complete);
#endif /* CONFIG_ADB_PMU */
-static u8 __pmac chrp_checksum(struct chrp_header* hdr)
+static u8 chrp_checksum(struct chrp_header* hdr)
{
u8 *ptr;
u16 sum = hdr->signature;
return sum;
}
-static u32 __pmac core99_calc_adler(u8 *buffer)
+static u32 core99_calc_adler(u8 *buffer)
{
int cnt;
u32 low, high;
return (high << 16) | low;
}
-static u32 __pmac core99_check(u8* datas)
+static u32 core99_check(u8* datas)
{
struct core99_header* hdr99 = (struct core99_header*)datas;
return hdr99->generation;
}
-static int __pmac sm_erase_bank(int bank)
+static int sm_erase_bank(int bank)
{
int stat, i;
unsigned long timeout;
return 0;
}
-static int __pmac sm_write_bank(int bank, u8* datas)
+static int sm_write_bank(int bank, u8* datas)
{
int i, stat = 0;
unsigned long timeout;
return 0;
}
-static int __pmac amd_erase_bank(int bank)
+static int amd_erase_bank(int bank)
{
int i, stat = 0;
unsigned long timeout;
return 0;
}
-static int __pmac amd_write_bank(int bank, u8* datas)
+static int amd_write_bank(int bank, u8* datas)
{
int i, stat = 0;
unsigned long timeout;
DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
}
-static void __pmac core99_nvram_sync(void)
+static void core99_nvram_sync(void)
{
struct core99_header* hdr99;
unsigned long flags;
lookup_partitions();
}
-int __pmac pmac_get_partition(int partition)
+int pmac_get_partition(int partition)
{
return nvram_partitions[partition];
}
-u8 __pmac pmac_xpram_read(int xpaddr)
+u8 pmac_xpram_read(int xpaddr)
{
int offset = nvram_partitions[pmac_nvram_XPRAM];
return ppc_md.nvram_read_val(xpaddr + offset);
}
-void __pmac pmac_xpram_write(int xpaddr, u8 data)
+void pmac_xpram_write(int xpaddr, u8 data)
{
int offset = nvram_partitions[pmac_nvram_XPRAM];
|(((unsigned long)(off)) & 0xFCUL) \
|1UL)
-static void volatile __iomem * __pmac
+static void volatile __iomem *
macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset)
{
unsigned int caddr;
return hose->cfg_data + offset;
}
-static int __pmac
+static int
macrisc_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
{
return PCIBIOS_SUCCESSFUL;
}
-static int __pmac
+static int
macrisc_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 val)
{
/*
* Verifiy that a specific (bus, dev_fn) exists on chaos
*/
-static int __pmac
+static int
chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
{
struct device_node *np;
return PCIBIOS_SUCCESSFUL;
}
-static int __pmac
+static int
chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
{
return macrisc_read_config(bus, devfn, offset, len, val);
}
-static int __pmac
+static int
chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 val)
{
+ (((unsigned long)bus) << 16) \
+ 0x01000000UL)
-static void volatile __iomem * __pmac
+static void volatile __iomem *
u3_ht_cfg_access(struct pci_controller* hose, u8 bus, u8 devfn, u8 offset)
{
if (bus == hose->first_busno) {
return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
}
-static int __pmac
+static int
u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
{
return PCIBIOS_SUCCESSFUL;
}
-static int __pmac
+static int
u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 val)
{
pcibios_fixup_OF_interrupts();
}
-int __pmac
+int
pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
{
struct device_node* node;
* Disable second function on K2-SATA, it's broken
* and disable IO BARs on first one
*/
-void __pmac pmac_pci_fixup_k2_sata(struct pci_dev* dev)
+void pmac_pci_fixup_k2_sata(struct pci_dev* dev)
{
int i;
u16 cmd;
};
/* Default addresses */
-static volatile struct pmac_irq_hw *pmac_irq_hw[4] __pmacdata = {
+static volatile struct pmac_irq_hw *pmac_irq_hw[4] = {
(struct pmac_irq_hw *) 0xf3000020,
(struct pmac_irq_hw *) 0xf3000010,
(struct pmac_irq_hw *) 0xf4000020,
#define OHARE_LEVEL_MASK 0x1ff00000
#define HEATHROW_LEVEL_MASK 0x1ff00000
-static int max_irqs __pmacdata;
-static int max_real_irqs __pmacdata;
-static u32 level_mask[4] __pmacdata;
+static int max_irqs;
+static int max_real_irqs;
+static u32 level_mask[4];
-static DEFINE_SPINLOCK(pmac_pic_lock __pmacdata);
+static DEFINE_SPINLOCK(pmac_pic_lock);
#define GATWICK_IRQ_POOL_SIZE 10
-static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE] __pmacdata;
+static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
/*
* Mark an irq as "lost". This is only used on the pmac
* since it can lose interrupts (see pmac_set_irq_mask).
* -- Cort
*/
-void __pmac
+void
__set_lost(unsigned long irq_nr, int nokick)
{
if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
}
}
-static void __pmac
+static void
pmac_mask_and_ack_irq(unsigned int irq_nr)
{
unsigned long bit = 1UL << (irq_nr & 0x1f);
spin_unlock_irqrestore(&pmac_pic_lock, flags);
}
-static void __pmac pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
+static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
{
unsigned long bit = 1UL << (irq_nr & 0x1f);
int i = irq_nr >> 5;
/* When an irq gets requested for the first client, if it's an
* edge interrupt, we clear any previous one on the controller
*/
-static unsigned int __pmac pmac_startup_irq(unsigned int irq_nr)
+static unsigned int pmac_startup_irq(unsigned int irq_nr)
{
unsigned long bit = 1UL << (irq_nr & 0x1f);
int i = irq_nr >> 5;
return 0;
}
-static void __pmac pmac_mask_irq(unsigned int irq_nr)
+static void pmac_mask_irq(unsigned int irq_nr)
{
clear_bit(irq_nr, ppc_cached_irq_mask);
pmac_set_irq_mask(irq_nr, 0);
mb();
}
-static void __pmac pmac_unmask_irq(unsigned int irq_nr)
+static void pmac_unmask_irq(unsigned int irq_nr)
{
set_bit(irq_nr, ppc_cached_irq_mask);
pmac_set_irq_mask(irq_nr, 0);
}
-static void __pmac pmac_end_irq(unsigned int irq_nr)
+static void pmac_end_irq(unsigned int irq_nr)
{
if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
&& irq_desc[irq_nr].action) {
extern struct smp_ops_t core99_smp_ops;
#endif /* CONFIG_SMP */
-static int __pmac
+static int
pmac_show_cpuinfo(struct seq_file *m)
{
struct device_node *np;
return 0;
}
-static int __openfirmware
+static int
pmac_show_percpuinfo(struct seq_file *m, int i)
{
#ifdef CONFIG_CPU_FREQ_PMAC
late_initcall(pmac_late_init);
/* can't be __init - can be called whenever a disk is first accessed */
-void __pmac
+void
note_bootable_part(dev_t dev, int part, int goodness)
{
static int found_boot = 0;
}
}
-static void __pmac
+static void
pmac_restart(char *cmd)
{
#ifdef CONFIG_ADB_CUDA
}
}
-static void __pmac
+static void
pmac_power_off(void)
{
#ifdef CONFIG_ADB_CUDA
}
}
-static void __pmac
+static void
pmac_halt(void)
{
pmac_power_off();
*/
static unsigned long psurge_smp_message[NR_CPUS];
-void __pmac psurge_smp_message_recv(struct pt_regs *regs)
+void psurge_smp_message_recv(struct pt_regs *regs)
{
int cpu = smp_processor_id();
int msg;
smp_message_recv(msg, regs);
}
-irqreturn_t __pmac psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
+irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
{
psurge_smp_message_recv(regs);
return IRQ_HANDLED;
}
-static void __pmac smp_psurge_message_pass(int target, int msg, unsigned long data,
+static void smp_psurge_message_pass(int target, int msg, unsigned long data,
int wait)
{
int i;
/* PowerSurge-style Macs */
-struct smp_ops_t psurge_smp_ops __pmacdata = {
+struct smp_ops_t psurge_smp_ops = {
.message_pass = smp_psurge_message_pass,
.probe = smp_psurge_probe,
.kick_cpu = smp_psurge_kick_cpu,
};
/* Core99 Macs (dual G4s) */
-struct smp_ops_t core99_smp_ops __pmacdata = {
+struct smp_ops_t core99_smp_ops = {
.message_pass = smp_openpic_message_pass,
.probe = smp_core99_probe,
.kick_cpu = smp_core99_kick_cpu,
#endif
}
-unsigned long __pmac
+unsigned long
pmac_get_rtc_time(void)
{
#if defined(CONFIG_ADB_CUDA) || defined(CONFIG_ADB_PMU)
return 0;
}
-int __pmac
+int
pmac_set_rtc_time(unsigned long nowtime)
{
#if defined(CONFIG_ADB_CUDA) || defined(CONFIG_ADB_PMU)
/*
* Reset the time after a sleep.
*/
-static int __pmac
+static int
time_sleep_notify(struct pmu_sleep_notifier *self, int when)
{
static unsigned long time_diff;
return PBOOK_SLEEP_OK;
}
-static struct pmu_sleep_notifier time_sleep_notifier __pmacdata = {
+static struct pmu_sleep_notifier time_sleep_notifier = {
time_sleep_notify, SLEEP_LEVEL_MISC,
};
#endif /* CONFIG_PM */
/* Tables for known hardware */
/* Motorola PowerStackII - Utah */
-static char Utah_pci_IRQ_map[23] __prepdata =
+static char Utah_pci_IRQ_map[23] =
{
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
0, /* Slot 22 - unused */
};
-static char Utah_pci_IRQ_routes[] __prepdata =
+static char Utah_pci_IRQ_routes[] =
{
0, /* Line 0 - Unused */
9, /* Line 1 */
/* Motorola PowerStackII - Omaha */
/* no integrated SCSI or ethernet */
-static char Omaha_pci_IRQ_map[23] __prepdata =
+static char Omaha_pci_IRQ_map[23] =
{
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
0,
};
-static char Omaha_pci_IRQ_routes[] __prepdata =
+static char Omaha_pci_IRQ_routes[] =
{
0, /* Line 0 - Unused */
9, /* Line 1 */
};
/* Motorola PowerStack */
-static char Blackhawk_pci_IRQ_map[19] __prepdata =
+static char Blackhawk_pci_IRQ_map[19] =
{
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
3, /* Slot P5 */
};
-static char Blackhawk_pci_IRQ_routes[] __prepdata =
+static char Blackhawk_pci_IRQ_routes[] =
{
0, /* Line 0 - Unused */
9, /* Line 1 */
};
/* Motorola Mesquite */
-static char Mesquite_pci_IRQ_map[23] __prepdata =
+static char Mesquite_pci_IRQ_map[23] =
{
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
};
/* Motorola Sitka */
-static char Sitka_pci_IRQ_map[21] __prepdata =
+static char Sitka_pci_IRQ_map[21] =
{
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
};
/* Motorola MTX */
-static char MTX_pci_IRQ_map[23] __prepdata =
+static char MTX_pci_IRQ_map[23] =
{
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
/* Motorola MTX Plus */
/* Secondary bus interrupt routing is not supported yet */
-static char MTXplus_pci_IRQ_map[23] __prepdata =
+static char MTXplus_pci_IRQ_map[23] =
{
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
0, /* Slot 22 - unused */
};
-static char Raven_pci_IRQ_routes[] __prepdata =
+static char Raven_pci_IRQ_routes[] =
{
0, /* This is a dummy structure */
};
/* Motorola MVME16xx */
-static char Genesis_pci_IRQ_map[16] __prepdata =
+static char Genesis_pci_IRQ_map[16] =
{
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
0, /* Slot 15 - unused */
};
-static char Genesis_pci_IRQ_routes[] __prepdata =
+static char Genesis_pci_IRQ_routes[] =
{
0, /* Line 0 - Unused */
10, /* Line 1 */
15 /* Line 4 */
};
-static char Genesis2_pci_IRQ_map[23] __prepdata =
+static char Genesis2_pci_IRQ_map[23] =
{
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
};
/* Motorola Series-E */
-static char Comet_pci_IRQ_map[23] __prepdata =
+static char Comet_pci_IRQ_map[23] =
{
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
0,
};
-static char Comet_pci_IRQ_routes[] __prepdata =
+static char Comet_pci_IRQ_routes[] =
{
0, /* Line 0 - Unused */
10, /* Line 1 */
};
/* Motorola Series-EX */
-static char Comet2_pci_IRQ_map[23] __prepdata =
+static char Comet2_pci_IRQ_map[23] =
{
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
0,
};
-static char Comet2_pci_IRQ_routes[] __prepdata =
+static char Comet2_pci_IRQ_routes[] =
{
0, /* Line 0 - Unused */
10, /* Line 1 */
* This is actually based on the Carolina motherboard
* -- Cort
*/
-static char ibm8xx_pci_IRQ_map[23] __prepdata = {
+static char ibm8xx_pci_IRQ_map[23] = {
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
0, /* Slot 2 - unused */
2, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */
};
-static char ibm8xx_pci_IRQ_routes[] __prepdata = {
+static char ibm8xx_pci_IRQ_routes[] = {
0, /* Line 0 - unused */
15, /* Line 1 */
15, /* Line 2 */
* a 6015 ibm board
* -- Cort
*/
-static char ibm6015_pci_IRQ_map[23] __prepdata = {
+static char ibm6015_pci_IRQ_map[23] = {
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
0, /* Slot 2 - unused */
2, /* Slot 22 - */
};
-static char ibm6015_pci_IRQ_routes[] __prepdata = {
+static char ibm6015_pci_IRQ_routes[] = {
0, /* Line 0 - unused */
13, /* Line 1 */
15, /* Line 2 */
/* IBM Nobis and Thinkpad 850 */
-static char Nobis_pci_IRQ_map[23] __prepdata ={
+static char Nobis_pci_IRQ_map[23] ={
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
0, /* Slot 2 - unused */
0, /* Slot 15 - unused */
};
-static char Nobis_pci_IRQ_routes[] __prepdata = {
+static char Nobis_pci_IRQ_routes[] = {
0, /* Line 0 - Unused */
13, /* Line 1 */
13, /* Line 2 */
* IBM RS/6000 43p/140 -- paulus
* XXX we should get all this from the residual data
*/
-static char ibm43p_pci_IRQ_map[23] __prepdata = {
+static char ibm43p_pci_IRQ_map[23] = {
0, /* Slot 0 - unused */
0, /* Slot 1 - unused */
0, /* Slot 2 - unused */
1, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */
};
-static char ibm43p_pci_IRQ_routes[] __prepdata = {
+static char ibm43p_pci_IRQ_routes[] = {
0, /* Line 0 - unused */
15, /* Line 1 */
15, /* Line 2 */
* are routed to OpenPIC inputs 5-8. These values are offset by
* 16 in the table to reflect the Linux kernel interrupt value.
*/
-struct powerplus_irq_list Powerplus_pci_IRQ_list __prepdata =
+struct powerplus_irq_list Powerplus_pci_IRQ_list =
{
{25, 26, 27, 28},
{21, 22, 23, 24}
* are routed to OpenPIC inputs 12-15. These values are offset by
* 16 in the table to reflect the Linux kernel interrupt value.
*/
-struct powerplus_irq_list Mesquite_pci_IRQ_list __prepdata =
+struct powerplus_irq_list Mesquite_pci_IRQ_list =
{
{24, 25, 26, 27},
{28, 29, 30, 31}
* This table represents the standard PCI swizzle defined in the
* PCI bus specification.
*/
-static unsigned char prep_pci_intpins[4][4] __prepdata =
+static unsigned char prep_pci_intpins[4][4] =
{
{ 1, 2, 3, 4}, /* Buses 0, 4, 8, ... */
{ 2, 3, 4, 1}, /* Buses 1, 5, 9, ... */
#define MIN_DEVNR 11
#define MAX_DEVNR 22
-static int __prep
+static int
prep_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
{
return PCIBIOS_SUCCESSFUL;
}
-static int __prep
+static int
prep_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 val)
{
void (*map_non0_bus)(struct pci_dev *); /* For boards with more than bus 0 devices. */
struct powerplus_irq_list *pci_irq_list; /* List of PCI MPIC inputs */
unsigned char secondary_bridge_devfn; /* devfn of secondary bus transparent bridge */
-} mot_info[] __prepdata = {
+} mot_info[] = {
{0x300, 0x00, 0x00, "MVME 2400", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
{0x010, 0x00, 0x00, "Genesis", Genesis_pci_IRQ_map, Genesis_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
{0x020, 0x00, 0x00, "Powerstack (Series E)", Comet_pci_IRQ_map, Comet_pci_IRQ_routes, NULL, NULL, 0x00},
}
/* cpuinfo code common to all IBM PReP */
-static void __prep
+static void
prep_ibm_cpuinfo(struct seq_file *m)
{
unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
}
}
-static int __prep
+static int
prep_gen_cpuinfo(struct seq_file *m)
{
prep_ibm_cpuinfo(m);
return 0;
}
-static int __prep
+static int
prep_sandalfoot_cpuinfo(struct seq_file *m)
{
unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
return 0;
}
-static int __prep
+static int
prep_thinkpad_cpuinfo(struct seq_file *m)
{
unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
return 0;
}
-static int __prep
+static int
prep_carolina_cpuinfo(struct seq_file *m)
{
unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
return 0;
}
-static int __prep
+static int
prep_tiger1_cpuinfo(struct seq_file *m)
{
unsigned int l2_reg = inb(PREP_IBM_L2INFO);
/* Used by all Motorola PReP */
-static int __prep
+static int
prep_mot_cpuinfo(struct seq_file *m)
{
unsigned int cachew = *((unsigned char *)CACHECRBA);
return 0;
}
-static void __prep
+static void
prep_restart(char *cmd)
{
#define PREP_SP92 0x92 /* Special Port 92 */
#undef PREP_SP92
}
-static void __prep
+static void
prep_halt(void)
{
local_irq_disable(); /* no interrupts */
/* Carrera is the power manager in the Thinkpads. Unfortunately not much is
* known about it, so we can't power down.
*/
-static void __prep
+static void
prep_carrera_poweroff(void)
{
prep_halt();
* somewhat in the IBM Carolina Technical Specification.
* -Hollis
*/
-static void __prep
+static void
utah_sig87c750_setbit(unsigned int bytenum, unsigned int bitnum, int value)
{
/*
udelay(100); /* important: let controller recover */
}
-static void __prep
+static void
prep_sig750_poweroff(void)
{
/* tweak the power manager found in most IBM PRePs (except Thinkpads) */
/* not reached */
}
-static int __prep
+static int
prep_show_percpuinfo(struct seq_file *m, int i)
{
/* PREP's without residual data will give incorrect values here */
/*
* IBM 3-digit status LED
*/
-static unsigned int ibm_statusled_base __prepdata;
+static unsigned int ibm_statusled_base;
-static void __prep
+static void
ibm_statusled_progress(char *s, unsigned short hex);
-static int __prep
+static int
ibm_statusled_panic(struct notifier_block *dummy1, unsigned long dummy2,
void * dummy3)
{
return NOTIFY_DONE;
}
-static struct notifier_block ibm_statusled_block __prepdata = {
+static struct notifier_block ibm_statusled_block = {
ibm_statusled_panic,
NULL,
INT_MAX /* try to do it first */
};
-static void __prep
+static void
ibm_statusled_progress(char *s, unsigned short hex)
{
static int notifier_installed;
todc_calibrate_decr();
}
-static unsigned int __prep
+static unsigned int
prep_irq_canonicalize(u_int irq)
{
if (irq == 2)
/*
* IDE stuff.
*/
-static int __prep
+static int
prep_ide_default_irq(unsigned long base)
{
switch (base) {
}
}
-static unsigned long __prep
+static unsigned long
prep_ide_default_io_base(int index)
{
switch (index) {
do_openpic_setup_cpu();
}
-static struct smp_ops_t prep_smp_ops __prepdata = {
+static struct smp_ops_t prep_smp_ops = {
smp_openpic_message_pass,
smp_prep_probe,
smp_prep_kick_cpu,
#include <asm/ide.h>
-unsigned char __res[sizeof(RESIDUAL)] __prepdata = {0,};
+unsigned char __res[sizeof(RESIDUAL)] = {0,};
RESIDUAL *res = (RESIDUAL *)&__res;
char * PnP_BASE_TYPES[] __initdata = {
* chrp only uses it during early boot.
*/
#ifdef CONFIG_XMON
-#define BTEXT __pmac
-#define BTDATA __pmacdata
+#define BTEXT
+#define BTDATA
#else
#define BTEXT __init
#define BTDATA __initdata
* changes.
*/
-void __openfirmware
+void
map_boot_text(void)
{
unsigned long base, offset, size;
static char nvramData[MAX_PREP_NVRAM];
static NVRAM_MAP *nvram=(NVRAM_MAP *)&nvramData[0];
-unsigned char __prep prep_nvram_read_val(int addr)
+unsigned char prep_nvram_read_val(int addr)
{
outb(addr, PREP_NVRAM_AS0);
outb(addr>>8, PREP_NVRAM_AS1);
return inb(PREP_NVRAM_DATA);
}
-void __prep prep_nvram_write_val(int addr,
+void prep_nvram_write_val(int addr,
unsigned char val)
{
outb(addr, PREP_NVRAM_AS0);
}
}
-__prep
-char __prep *prep_nvram_get_var(const char *name)
+char *prep_nvram_get_var(const char *name)
{
char *cp;
int namelen;
return NULL;
}
-__prep
-char __prep *prep_nvram_first_var(void)
+char *prep_nvram_first_var(void)
{
if (nvram->Header.GELength == 0) {
return NULL;
}
}
-__prep
-char __prep *prep_nvram_next_var(char *name)
+char *prep_nvram_next_var(char *name)
{
char *cp;
extern boot_infos_t *boot_infos;
unsigned long dev_tree_size;
-void __openfirmware
+void
phys_call_rtas(int service, int nargs, int nret, ...)
{
va_list list;
/*
* Returns all nodes linked together
*/
-struct device_node * __openfirmware
+struct device_node *
find_all_nodes(void)
{
struct device_node *head, **prevp, *np;
/*
* Add a property to a node
*/
-void __openfirmware
+void
prom_add_property(struct device_node* np, struct property* prop)
{
struct property **next = &np->properties;
}
/* I quickly hacked that one, check against spec ! */
-static inline unsigned long __openfirmware
+static inline unsigned long
bus_space_to_resource_flags(unsigned int bus_space)
{
u8 space = (bus_space >> 24) & 0xf;
}
}
-static struct resource* __openfirmware
+static struct resource*
find_parent_pci_resource(struct pci_dev* pdev, struct address_range *range)
{
unsigned long mask;
* or other nodes attached to the root node. Ultimately, put some
* link to resources in the OF node.
*/
-struct resource* __openfirmware
+struct resource*
request_OF_resource(struct device_node* node, int index, const char* name_postfix)
{
struct pci_dev* pcidev;
return NULL;
}
-int __openfirmware
+int
release_OF_resource(struct device_node* node, int index)
{
struct pci_dev* pcidev;
}
#if 0
-void __openfirmware
+void
print_properties(struct device_node *np)
{
struct property *pp;
static DEFINE_SPINLOCK(rtas_lock);
/* this can be called after setup -- Cort */
-int __openfirmware
+int
call_rtas(const char *service, int nargs, int nret,
unsigned long *outputs, ...)
{
projects / linux-2.6-omap-h63xx.git / commitdiff