*
* Finds 'best' divider value in an array based on the source and target
* rates. The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
*
* Returns the rounded clock rate or returns 0xffffffff on error.
*/
* Compatibility wrapper for OMAP clock framework
* Finds best target rate based on the source clock and possible dividers.
* rates. The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
*
* Returns the rounded clock rate or returns 0xffffffff on error.
*/
pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
- /* CONFIG_PARTICIPANT clocks are changed only in sets via the
- rate table mechanism, driven by mpu_speed */
- if (clk->flags & CONFIG_PARTICIPANT)
- return -EINVAL;
-
- /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
if (clk->set_rate != NULL)
ret = clk->set_rate(clk, rate);
{
u32 field_val, v, parent_div;
- if (clk->flags & CONFIG_PARTICIPANT)
- return -EINVAL;
-
if (!clk->clksel)
return -EINVAL;
.parent = &core_ck,
.prcm_mod = MPU_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- ALWAYS_ENABLED | DELAYED_APP |
- CONFIG_PARTICIPANT,
+ ALWAYS_ENABLED | DELAYED_APP,
.clkdm = { .name = "mpu_clkdm" },
.init = &omap2_init_clksel_parent,
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
.clksel = mpu_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
/*
.name = "dsp_fck",
.parent = &core_ck,
.prcm_mod = OMAP24XX_DSP_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
- CONFIG_PARTICIPANT,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP,
.clkdm = { .name = "dsp_clkdm" },
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
.clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
.clksel = dsp_fck_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
/* DSP interface clock */
.parent = &dsp_fck,
.prcm_mod = OMAP24XX_DSP_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
- CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
+ PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "dsp_clkdm" },
.clksel_reg = CM_CLKSEL,
.clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
.clksel = dsp_irate_ick_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
/* 2420 only */
.name = "dsp_ick", /* apparently ipi and isp */
.parent = &dsp_irate_ick,
.prcm_mod = OMAP24XX_DSP_MOD,
- .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
+ .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
.clkdm = { .name = "dsp_clkdm" },
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
.name = "iva2_1_ick",
.parent = &dsp_irate_ick,
.prcm_mod = OMAP24XX_DSP_MOD,
- .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+ .flags = CLOCK_IN_OMAP243X | DELAYED_APP,
.clkdm = { .name = "dsp_clkdm" },
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
.name = "iva1_ifck",
.parent = &core_ck,
.prcm_mod = OMAP24XX_DSP_MOD,
- .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | DELAYED_APP,
+ .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
.clkdm = { .name = "iva1_clkdm" },
.enable_reg = CM_FCLKEN,
.enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
.parent = &core_ck,
.prcm_mod = CORE_MOD,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- ALWAYS_ENABLED | DELAYED_APP |
- CONFIG_PARTICIPANT,
+ ALWAYS_ENABLED | DELAYED_APP,
.clkdm = { .name = "core_l3_clkdm" },
.clksel_reg = CM_CLKSEL1,
.clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
.clksel = core_l3_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
/* usb_l4_ick */
.name = "usb_l4_ick",
.parent = &core_l3_ck,
.prcm_mod = CORE_MOD,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- DELAYED_APP | CONFIG_PARTICIPANT | WAIT_READY,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY |
+ DELAYED_APP,
.clkdm = { .name = "core_l4_clkdm" },
.enable_reg = CM_ICLKEN2,
.enable_bit = OMAP24XX_EN_USB_SHIFT,
.clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
.clksel = usb_l4_ick_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
/*
* divided value of fclk.
*
*/
-/* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
+/* XXX REVISIT: GFX clock is part of the table rate set also? doublecheck. */
/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
static const struct clksel gfx_fck_clksel[] = {
.name = "mdm_ick",
.parent = &core_ck,
.prcm_mod = OMAP2430_MDM_MOD,
- .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+ .flags = CLOCK_IN_OMAP243X | DELAYED_APP,
.clkdm = { .name = "mdm_clkdm" },
.enable_reg = CM_ICLKEN,
.enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
.clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
.clksel = mdm_ick_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
static struct clk mdm_osc_ck = {