]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[ARM] 4596/1: S3C2412: Correct IRQs for SDI+CF and add decoding support
authorBen Dooks <ben-linux@fluff.org>
Thu, 4 Oct 2007 20:41:20 +0000 (21:41 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Fri, 12 Oct 2007 22:43:42 +0000 (23:43 +0100)
Fix the IRQ numbers of the CF and SDI interface on the S3C2412
and S3C2413. Add support to handle these IRQs properly and
ensure that the SDI controller platform device is correctly
renumbered.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mach-s3c2412/irq.c
arch/arm/mach-s3c2412/s3c2412.c
include/asm-arm/arch-s3c2410/irqs.h

index f0d66828f96576768c4f6ab7d0bb696c31489858..e9d0c769f5da2e576891953d27f8f6d18c477714 100644 (file)
@@ -38,6 +38,9 @@
 #include <asm/plat-s3c24xx/irq.h>
 #include <asm/plat-s3c24xx/pm.h>
 
+#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
+#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
+
 /* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
  * having them turn up in both the INT* and the EINT* registers. Whilst
  * both show the status, they both now need to be acked when the IRQs
@@ -105,6 +108,51 @@ static struct irq_chip s3c2412_irq_eint0t4 = {
        .set_type  = s3c_irqext_type,
 };
 
+#define INTBIT(x)      (1 << ((x) - S3C2410_IRQSUB(0)))
+
+/* CF and SDI sub interrupts */
+
+static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
+{
+       unsigned int subsrc, submsk;
+
+       subsrc = __raw_readl(S3C2410_SUBSRCPND);
+       submsk = __raw_readl(S3C2410_INTSUBMSK);
+
+       subsrc  &= ~submsk;
+
+       if (subsrc & INTBIT(IRQ_S3C2412_SDI))
+               desc_handle_irq(IRQ_S3C2412_SDI, irq_desc + IRQ_S3C2412_SDI);
+
+       if (subsrc & INTBIT(IRQ_S3C2412_CF))
+               desc_handle_irq(IRQ_S3C2412_CF, irq_desc + IRQ_S3C2412_CF);
+}
+
+#define INTMSK_CFSDI   (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
+#define SUBMSK_CFSDI   INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
+
+static void s3c2412_irq_cfsdi_mask(unsigned int irqno)
+{
+       s3c_irqsub_mask(irqno, INTMSK_CFSDI, SUBMSK_CFSDI);
+}
+
+static void s3c2412_irq_cfsdi_unmask(unsigned int irqno)
+{
+       s3c_irqsub_unmask(irqno, INTMSK_CFSDI);
+}
+
+static void s3c2412_irq_cfsdi_ack(unsigned int irqno)
+{
+       s3c_irqsub_maskack(irqno, INTMSK_CFSDI, SUBMSK_CFSDI);
+}
+
+static struct irq_chip s3c2412_irq_cfsdi = {
+       .name           = "s3c2412-cfsdi",
+       .ack            = s3c2412_irq_cfsdi_ack,
+       .mask           = s3c2412_irq_cfsdi_mask,
+       .unmask         = s3c2412_irq_cfsdi_unmask,
+};
+
 static int s3c2412_irq_add(struct sys_device *sysdev)
 {
        unsigned int irqno;
@@ -115,6 +163,16 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
                set_irq_flags(irqno, IRQF_VALID);
        }
 
+       /* add demux support for CF/SDI */
+
+       set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
+
+       for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
+               set_irq_chip(irqno, &s3c2412_irq_cfsdi);
+               set_irq_handler(irqno, handle_level_irq);
+               set_irq_flags(irqno, IRQF_VALID);
+       }
+
        return 0;
 }
 
index e0ccb404623f738b373ee3eb227dc987e0b17808..4f92a1562d77fa62043e5d4a29679a8d928a612d 100644 (file)
@@ -78,6 +78,11 @@ void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
        s3c_device_lcd.name  = "s3c2412-lcd";
        s3c_device_nand.name = "s3c2412-nand";
 
+       /* alter IRQ of SDI controller */
+
+       s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
+       s3c_device_sdi.resource[1].end   = IRQ_S3C2412_SDI;
+
        /* spi channel related changes, s3c2412/13 specific */
        s3c_device_spi0.name = "s3c2412-spi";
        s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
index 3b49cd1c345c281ee3cd09dcdf8e7b308fe02587..996f65488d2d01dc2f8c85d6879ce088e1b74ea8 100644 (file)
 #define IRQ_TC                 S3C2410_IRQSUB(9)
 #define IRQ_ADC                        S3C2410_IRQSUB(10)
 
+/* extra irqs for s3c2412 */
+
+#define IRQ_S3C2412_CFSDI      S3C2410_IRQ(21)
+
+#define IRQ_S3C2412_SDI                S3C2410_IRQSUB(13)
+#define IRQ_S3C2412_CF         S3C2410_IRQSUB(14)
+
 /* extra irqs for s3c2440 */
 
 #define IRQ_S3C2440_CAM_C      S3C2410_IRQSUB(11)      /* S3C2443 too */