#define DPLL_LOW_POWER_BYPASS 0x5
#define DPLL_LOCKED 0x7
+#define _OMAP34XX_PRM_REGADDR(module, reg) \
+ ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
+
#define OMAP3430_PRM_CLKSRC_CTRL \
- OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+ _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
#define OMAP3430_PRM_CLKSEL \
- OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
+ _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
#define OMAP3430_PRM_CLKOUT_CTRL \
- OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
+ _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
/* PRM CLOCKS */