* Start transmit. Caller is responsible for locking shared resources.
* pThis must be locked.
*/
-void musb_h_tx_start(struct musb *pThis, u8 bEnd)
+static inline void musb_h_tx_start(struct musb_hw_ep *ep)
{
- u16 wCsr;
- void __iomem *pBase = pThis->pRegs;
+ u16 txcsr;
- /* NOTE: no locks here; caller should lock */
- MGC_SelectEnd(pBase, bEnd);
- if (bEnd) {
- wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
- wCsr |= MGC_M_TXCSR_TXPKTRDY | MGC_M_TXCSR_H_WZC_BITS;
- DBG(5, "Writing TXCSR%d = %x\n", bEnd, wCsr);
- MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd, wCsr);
+ /* NOTE: no locks here; caller should lock and select EP */
+ if (ep->bLocalEnd) {
+ txcsr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
+ txcsr |= MGC_M_TXCSR_TXPKTRDY | MGC_M_TXCSR_H_WZC_BITS;
+ musb_writew(ep->regs, MGC_O_HDRC_TXCSR, txcsr);
} else {
- wCsr = MGC_M_CSR0_H_SETUPPKT | MGC_M_CSR0_TXPKTRDY;
- MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsr);
+ txcsr = MGC_M_CSR0_H_SETUPPKT | MGC_M_CSR0_TXPKTRDY;
+ musb_writew(ep->regs, MGC_O_HDRC_CSR0, txcsr);
}
}
-#ifdef CONFIG_USB_TI_CPPI_DMA
-
-void cppi_hostdma_start(struct musb *pThis, u8 bEnd)
+static inline void cppi_host_txdma_start(struct musb_hw_ep *ep)
{
- void __iomem *pBase = pThis->pRegs;
- u16 txCsr;
+ u16 txcsr;
- /* NOTE: no locks here; caller should lock */
- MGC_SelectEnd(pBase, bEnd);
- txCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
- txCsr |= MGC_M_TXCSR_DMAENAB | MGC_M_TXCSR_H_WZC_BITS;
- MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd, txCsr);
+ /* NOTE: no locks here; caller should lock and select EP */
+ txcsr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
+ txcsr |= MGC_M_TXCSR_DMAENAB | MGC_M_TXCSR_H_WZC_BITS;
+ musb_writew(ep->regs, MGC_O_HDRC_TXCSR, txcsr);
}
-#endif
-
/*
* Start the URB at the front of an endpoint's queue
* end must be claimed from the caller.
if ((urb->transfer_flags & URB_ISO_ASAP)
|| (wFrame >= urb->start_frame)) {
/* REVISIT the SOF irq handler shouldn't duplicate
- * this code... or the branch below...
- * ... and we don't set urb->start_frame
+ * this code; and we don't init urb->start_frame...
*/
qh->frame = 0;
- printk("Start --> periodic TX%s on %d\n",
- pEnd->tx_channel ? " DMA" : "",
- bEnd);
- if (!pEnd->tx_channel)
- musb_h_tx_start(musb, bEnd);
- else
- cppi_hostdma_start(musb, bEnd);
+ goto start;
} else {
qh->frame = urb->start_frame;
/* enable SOF interrupt so we can count down */
}
break;
default:
+start:
DBG(4, "Start TX%d %s\n", bEnd,
pEnd->tx_channel ? "dma" : "pio");
if (!pEnd->tx_channel)
- musb_h_tx_start(musb, bEnd);
- else
- cppi_hostdma_start(musb, bEnd);
+ musb_h_tx_start(pEnd);
+ else if (is_cppi_enabled())
+ cppi_host_txdma_start(pEnd);
}
}
* Program an HDRC endpoint as per the given URB
* Context: irqs blocked, controller lock held
*/
-#define MGC_M_TXCSR_ISO 0 /* FIXME */
static void musb_ep_program(struct musb *pThis, u8 bEnd,
struct urb *pUrb, unsigned int is_out,
u8 * pBuffer, u32 dwLength)
{
-#ifndef CONFIG_USB_INVENTRA_FIFO
- struct dma_controller *pDmaController;
- struct dma_channel *pDmaChannel;
- u8 bDmaOk;
-#endif
- void __iomem *pBase = pThis->pRegs;
+ struct dma_controller *pDmaController;
+ struct dma_channel *pDmaChannel;
+ u8 bDmaOk;
+ void __iomem *pBase = pThis->pRegs;
struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
struct musb_qh *qh;
u16 wPacketSize;
MGC_SelectEnd(pBase, bEnd);
-#ifndef CONFIG_USB_INVENTRA_FIFO
- pDmaChannel = is_out ? pEnd->tx_channel : pEnd->rx_channel;
+ /* candidate for DMA? */
pDmaController = pThis->pDmaController;
-
- /* candidate for DMA */
if (is_dma_capable() && bEnd && pDmaController) {
- bDmaOk = 1;
- if (bDmaOk && !pDmaChannel) {
+ pDmaChannel = is_out ? pEnd->tx_channel : pEnd->rx_channel;
+ if (!pDmaChannel) {
pDmaChannel = pDmaController->channel_alloc(
pDmaController, pEnd, is_out);
if (is_out)
pEnd->rx_channel = pDmaChannel;
}
} else
- bDmaOk = 0;
-#endif /* PIO isn't the only option */
+ pDmaChannel = NULL;
/* make sure we clear DMAEnab, autoSet bits from previous run */
csr &= ~(MGC_M_TXCSR_H_NAKTIMEOUT
| MGC_M_TXCSR_DMAMODE
| MGC_M_TXCSR_FRCDATATOG
- | MGC_M_TXCSR_ISO
| MGC_M_TXCSR_H_RXSTALL
| MGC_M_TXCSR_H_ERROR
| MGC_M_TXCSR_FIFONOTEMPTY
);
csr |= MGC_M_TXCSR_MODE;
- if (qh->type == USB_ENDPOINT_XFER_ISOC)
- csr |= MGC_M_TXCSR_ISO;
- else if (usb_gettoggle(pUrb->dev,
+ if (usb_gettoggle(pUrb->dev,
qh->epnum, 1))
csr |= MGC_M_TXCSR_H_WR_DATATOGGLE
| MGC_M_TXCSR_H_DATATOGGLE;
wLoadCount = min((u32) wPacketSize, dwLength);
#ifdef CONFIG_USB_INVENTRA_DMA
- if (bDmaOk && pDmaChannel) {
+ if (pDmaChannel) {
/* clear previous state */
wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
pDmaChannel = pEnd->pDmaChannel = NULL;
}
}
-#elif defined(CONFIG_USB_TI_CPPI_DMA)
+#endif
/* candidate for DMA */
- if (bDmaOk && pDmaChannel) {
+ if (is_cppi_enabled() && pDmaChannel) {
/* program endpoint CSRs first, then setup DMA.
* assume CPPI setup succeeds.
*/
}
}
-#endif
+
if (wLoadCount) {
/* ASSERT: TXCSR_DMAENAB was already cleared */
}
/* kick things off */
-#ifdef CONFIG_USB_TI_CPPI_DMA
+
+ if (is_cppi_enabled()) {
/* candidate for DMA */
if (pDmaChannel) {
pDmaChannel->dwActualLength = 0L;
} else
csr |= MGC_M_RXCSR_DMAENAB;
}
-#endif
+ }
+
csr |= MGC_M_RXCSR_H_REQPKT;
DBG(7, "RXCSR%d := %04x\n", bEnd, csr);
musb_writew(pEnd->regs, MGC_O_HDRC_RXCSR, csr);